Справочник по мощным TMOS транзисторам (MOTOROLA)

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4–808

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

= 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

= 0, I

= 250 µAdc)

Temperature Coefficient (positive)

(BR)DSS

100

—

110

—

Vdc

mV/°C

Zero Gate Voltage Drain Current

= 100 V, V

= 0)°

= 100 V, V

= 0, T

= 150°C)

DSS

—

100

µA

Gate–Body Leakage Current, Forward (V

GSF

= 20 Vdc, V

= 0) I

GSSF

— — 100 nAdc

Gate–Body Leakage Current, Reverse (V

GSR

= 20 Vdc, V

= 0) I

GSSR

— — 100 nAdc

ON CHARACTERISTICS*

Gate Threshold Voltage

= V

, I

= 250 µAdc)

Temperature Coefficient (negative)µ

GS(th)

2.0

—

3.0

6.0

4.0

—

Vdc

mV/°C

Static Drain–Source On–Resistance (V

= 10 Vdc, I

= 6.0 Adc) R

DS(on)

— 0.125 0.16 Ohm

Drain–Source On–Voltage (V

= 10 Vdc)

= 12 Adc)°

= 6.0 Adc, T

= 150°C)

DS(on)

—

1.5

1.4

2.4

1.92

Vdc

Forward Transconductance (V

≥ 15 V, I

= 6.0 A)

4.0 5.0 — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

25 V, V

iss

— 600 — pF

Reverse Transfer Capacitance

f = 1.0 MHz)

SFi 14

rss

— 70 —

Output Capacitance

ee Figure 14

oss

— 230 —

SWITCHING CHARACTERISTICS (T

= 100°C)

Turn–On Delay Time t

d(on)

— 10 — ns

Rise Time

= 50 V, I

= 12 A,

=10VR

=12Ω)

— 64 —

Turn–Off Delay Time

Ω)

See Figure 7

d(off)

— 21 —

Fall Time t

— 30 —

Gate Charge Q

— 18 26 nC

= 80 V, I

= 12 A,

= 10 Vdc)

— 4.0 —

Vdc)

See Figures 5 and 6

— 10 —

— 8.0 —

SOURCE–DRAIN DIODE CHARACTERISTICS*

Forward On–Voltage

= 12 A, V

= 0)

— 1.0 2.5 Vdc

(

SGS

)

= 12 A, V

= 0, T

= 150°C)

— 0.83 —

Reverse Recovery Time (I

= 12 A, V

= 0,

/dt = 100 A/µs, V

= 50 V)

— 110 — ns

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the contact screw on tab to center of die)″

(Measured from the drain lead 0.25″ from package to center of die)

—

3.5

4.5

—

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

— 7.5 —

*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.

4–809

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

Figure 3. On–Resistance versus Drain Current

, JUNCTION TEMPERATURE (°C)

Figure 4. On–Resistance Variation

with Temperature

Figure 5. Gate Charge Test Circuit

, DRAIN–TO–SOURCE VOLTAGE (VOLTS) V

, GATE–TO–SOURCE VOLTAGE (VOLTS)

, DRAIN CURRENT (AMPS)

, D

N C

URRE

(

AMPS

DS(on)

, D

–T

–

ANC

(

)

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

SAME

DEVICE

TYPE

AS DUT

+18 V V

10 V

100 k

0.1 µF

FERRITE

BEAD

DUT

100

2N3904

47 k

15 V

100 k

= 15 V

; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%.

1mA

47 k

, DRAIN CURRENT (AMPS)

43210

= 25°C

= 10 V

9 V

8 V

7 V

6 V

5 V

86420

≥ 15 V

= –55°C

25°C

100°C

0.6

0.5

0.2

0.3

0.4

0.1

24211815129630

2.2

1.8

1.6

1.4

1.2

0.8

0.6

–50 –25 0 25 50 75 100 125 150 175

= 10 V

= 6 A

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

, GATE–TO–SOURCE VOLTAGE (VOLTS)

100

0 5 10 15 20 25

, TOTAL GATE CHARGE (nC)

Figure 6. Gate–To–Source and

Drain–To–Source Voltage versus Gate Charge

= 100°C

25°C

–55°C

= 12 A

= 80 V

= 25°C

4–810

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA INFORMATION

FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum drain–to–source

voltage and drain current that a device can safely handle

when it is forward biased, or when it is on, or being turned on.

Because these curves include the limitations of simultaneous

high voltage and high current, up to the rating of the device,

they are especially useful to designers of linear systems. The

curves are based on a case temperature of 25°C and a maxi-

mum junction temperature of 175°C. Limitations for repetitive

pulses at various case temperatures can be determined by

using the thermal response curves. Motorola Application

Note, AN569, “Transient Thermal Resistance–General Data

and Its Use” provides detailed instructions.

SWITCHING SAFE OPERATING AREA

The switching safe operating area (SOA) of Figure 9 is the

boundary that the load line may traverse without incurring

damage to the MOSFET. The fundamental limits are the

peak current, I

and the breakdown voltage, BV

DSS

. The

switching SOA shown in Figure 9 is applicable for both turn–

on and turn–off of the devices for switching times less than

one microsecond.

The power averaged over a complete switching cycle must

be less than:

J(max)

– T

θJC

Figure 7. Resistive Switching Time

versus Gate Resistance

(

)

, GATE RESISTANCE (OHMS)

= 50 V

= 12 A

= 10 V

= 25°C

d(off)

d(on)

100010010

000

100

, DRAIN CURRENT (AMPS)

, D

N C

URRE

(

AMPS

)

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Forward Biased

Safe Operating Area

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 9. Maximum Rated Switching

Safe Operating Area

0 20 40 60 80 100

Figure 10. Thermal Response

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

0.1

100

DS(on)

LIMIT

THERMAL LIMIT

PACKAGE LIMIT

= 20 V

SINGLE PULSE

= 25°C

000

0.1

100 µs

1 ms

10 ms

θJC

(t) = r(t) R

θJC

= 1.9°C/W MAX

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t

J(pk)

– T

= P

(pk)

θJC

(t)

(pk)

DUTY CYCLE, D = t

t, TIME (ms)

0.01

D = 0.5

0.05

0.01

SINGLE PULSE

0.01

0.02

120

100

≤ 175°C

0.03

0.02

0.05

0.1

0.2

0.3

0.5

0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000

OPERATION LIMITED IN THIS

AREA BY R

DS(on)

0.1

0.2

4–811

Motorola TMOS Power MOSFET Transistor Device Data

COMMUTATING SAFE OPERATING AREA (CSOA)

The Commutating Safe Operating Area (CSOA) of Figure

12 defines the limits of safe operation for commutated sour-

ce-drain current versus re-applied drain voltage when the

source-drain diode has undergone forward bias. The curve

shows the limitations of I

and peak V

for a given rate of

change of source current. It is applicable when waveforms

similar to those of Figure 11 are present. Full or half-bridge

PWM DC motor controllers are common applications requir-

ing CSOA data.

Device stresses increase with increasing rate of change of

source current so dI

/dt is specified with a maximum value.

Higher values of dI

/dt require an appropriate derating of I

peak V

or both. Ultimately dI

/dt is limited primarily by de-

vice, package, and circuit impedances. Maximum device

stress occurs during t

as the diode goes from conduction to

reverse blocking.

DS(pk)

is the peak drain–to–source voltage that the device

must sustain during commutation; I

is the maximum for-

ward source-drain diode current just prior to the onset of

commutation.

is specified at rated BV

DSS

to ensure that the CSOA

stress is maximized as I

decays from I

to zero.

should be minimized during commutation. T

has only

a second order effect on CSOA.

Stray inductances in Motorola’s test circuit are assumed to

be practical minimums.

Figure 11. Commutating Waveforms

15 V

90%

/dt

10%

dsL

/dt

DS(pk)

MAX. CSOA

STRESS AREA

0.25 I

Figure 12. Commutating Safe Operating

Area (CSOA)

200

020406080

, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

–

Figure 13. Commutating Safe Operating Area

Test Circuit

20 V

DUT

= 80% OF RATED BV

DSS

dsL

= V

+ L

⋅ dl

/dt

–

≤ 175°C

= 12 A

dIs/dt ≤ 100 A/µs

≤ 100 V

100

120 140 160 180

, SOURCE–TO–DRAIN CURRENT (AMPS)

4–812

Motorola TMOS Power MOSFET Transistor Device Data

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 14. Capacitance Variation

C, CAPACITANCE (pF)

= 0 V

iss

oss

rss

2000

1500

1000

500

60453015015

Figure 15. Maximum Avalanche Energy versus

Starting Junction Temperature

, STARTING JUNCTION TEMPERATURE (°C)

300

25 50

250

200

150

100

75 100 125 150 175

PEAK I

= 12 A

= 25 V

Figure 16. Unclamped Inductive Switching

Test Circuit

Figure 17. Unclamped Inductive Switching

Waveforms

DSS

L(t)

t, (TIME)

, SINGLE PULSE AVALANCHE ENERGY (mJ)E

4–813

Motorola TMOS Power MOSFET Transistor Device Data



P–Channel Enhancement–Mode Silicon Gate

This TMOS Power FET is designed for medium voltage, high

speed power switching applications such as switching regulators,

converters, solenoid and relay drivers.

• Silicon Gate for Fast Switching Speeds — Switching Times

Specified at 100°C

• Designer’s Data — I

DSS

, V

DS(on)

, V

GS(th)

and SOA Specified

at Elevated Temperature

• Rugged — SOA is Power Dissipation Limited

• Source–to–Drain Diode Characterized for Use With Inductive Loads

MAXIMUM RATINGS

= 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain–Source Voltage V

DSS

100 Vdc

Drain–Gate Voltage (R

= 1.0 MΩ) V

DGR

100 Vdc

Gate–Source Voltage — Continuous

Gate–Source Voltage — Non–repetitive (t

≤ 50 µs)

GSM

±20

±40

Vdc

Vpk

Drain Current — Continuous

Drain Current — Pulsed

Adc

Total Power Dissipation

Derate above 25°C

0.6

Watts

W/°C

Operating and Storage Temperature Range T

, T

stg

–65 to 150 °C

THERMAL CHARACTERISTICS

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient°

θJC

θJA

1.67

62.5

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

260 °C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

REV 1

SEMICONDUCTOR TECHNICAL DATA

TMOS POWER FET

12 AMPERES

100 VOLTS

DS(on)

= 0.3 OHM



CASE 221A–06, Style 5

TO–220AB

4–814

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

= 25°C unless otherwise noted)

Characteristic

Symbol Min Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

= 0, I

= 0.25 mA)

(BR)DSS

100 — Vdc

Zero Gate Voltage Drain Current

= Rated V

DSS

, V

= 0)

= Rated V

DSS

, V

= 0, T

= 125°C)

DSS

—

100

µAdc

Gate–Body Leakage Current, Forward (V

GSF

= 20 Vdc, V

= 0) I

GSSF

— 100 nAdc

Gate–Body Leakage Current, Reverse (V

GSR

= 20 Vdc, V

= 0) I

GSSR

— 100 nAdc

ON CHARACTERISTICS*

Gate Threshold Voltage (V

= V

, I

= 1.0 mA)

= 100°C

GS(th)

2.0

1.5

4.5

4.0

Vdc

Static Drain–Source On–Resistance (V

= 10 Vdc, I

= 6.0 Adc) R

DS(on)

— 0.3 Ohm

Drain–Source On–Voltage (V

= 10 V)

= 12 Adc)

= 6.0 Adc, T

= 100°C)

DS(on)

—

4.2

3.8

Vdc

Forward Transconductance (V

= 15 V, I

= 6.0 A) g

2.0 — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

25 V, V

iss

— 920 pF

Output Capacitance

f = 1.0 MHz)

SFi 10

oss

— 575

Reverse Transfer Capacitance

gure 10

rss

— 200

SWITCHING CHARACTERISTICS* (T

= 100°C)

Turn–On Delay Time t

d(on)

— 50 ns

Rise Time

= 25 V, I

= 0.5 Rated I

=50Ω)

— 150

Turn–Off Delay Time

Ω)

See Figures 12 and 13

d(off)

— 150

Fall Time t

— 150

Total Gate Charge

0.8 Rated V

DSS

33 (Typ) 50 nC

Gate–Source Charge

Rated

DSS

= Rated I

, V

= 10 V)

SFi 11

16 (Typ) —

Gate–Drain Charge

gure 11

17 (Typ) —

SOURCE–DRAIN DIODE CHARACTERISTICS*

Forward On–Voltage

(I RtdI

4.0 (Typ) 5.5 Vdc

Forward Turn–On Time

= Rated I

= 0

)

Limited by stray inductance

Reverse Recovery Time

300 (Typ) — ns

INTERNAL PACKAGE INDUCTANCE (TO–204)

Internal Drain Inductance

(Measured from the contact screw on the header closer

to the source pin and the center of the die)

5.0 (Typ) —

Internal Source Inductance

(Measured from the source pin, 0.25″ from the package

to the source bond pad)

12.5 (Typ) —

INTERNAL PACKAGE INDUCTANCE (TO–220)

Internal Drain Inductance

(Measured from the contact screw on tab to center of die)

(Measured from the drain lead 0.25″ from package to center of die)

3.5 (Typ)

4.5 (Typ)

—

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

7.5 (Typ) —

*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

4–815

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

–V

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

, JUNCTION TEMPERATURE (°C)

Figure 2. Gate–Threshold Voltage Variation

With Temperature

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 3. Transfer Characteristics

, JUNCTION TEMPERATURE (°C)

Figure 4. Normalized Breakdown Voltage

versus Temperature

, DRAIN CURRENT (AMPS)

Figure 5. On–Resistance versus Drain Current

, JUNCTION TEMPERATURE (°C)

Figure 6. On–Resistance Variation

With Temperature

–I

, D

N C

URRE

(

AMPS

DS(on)

, D

–T

–

ANC

(

)

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

, D

N C

URRE

(

AMPS

)

GS(th)

, GATE THRESHOLD VOLTAGE (NORMALIZED)

BR(DSS)

, DRAIN–TO–SOURCE BREAKDOWN VOLTAGE

(NORMALIZED)

109876543210

1.2

1.1

0.9

0.8

–50 –25 0 25 50 75 100 125 150

201612840

1.6

1.2

0.8

0.4

–50 –75 0 25 50 75 100 125 150

0.5

0.4

0.3

0.2

0.1

4036322824201612840

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

–50 –25 0 25 50 75 100 125 150

= 25°C

= –20 V

8 V

10 V

7 V

6 V

5 V

= V

= 1 mA

= 20 V

= –55°C

25°C

100°C

= 0

= 0.25 mA

= 100°C

25°C

–55°C

= 15 V

= 10 V

= 6 A

4–816

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA INFORMATION

, DRAIN CURRENT (AMPS)

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased

Safe Operating Area

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Switching

Safe Operating Area

020406080

100

DS(on)

LIMIT

PACKAGE LIMIT

THERMAL LIMIT

= 20 V

SINGLE PULSE

= 25°C

10 µs

1 ms

10 ms

100

0.1 ms

MTM/MTP12P06

MTM/MTP12P10

10 30 50 70 90

MTM/MTP12P06

MTM/MTP12P10

FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum drain–to–source

voltage and drain current that a device can safely handle

when it is forward biased, or when it is on, or being turned on.

Because these curves include the limitations of simultaneous

high voltage and high current, up to the rating of the device,

they are especially useful to designers of linear systems. The

curves are based on a case temperature of 25°C and a maxi-

mum junction temperature of 150°C. Limitations for repetitive

pulses at various case temperatures can be determined by

using the thermal response curves. Motorola Application

Note, AN569, “Transient Thermal Resistance–General Data

and Its Use” provides detailed instructions.

SWITCHING SAFE OPERATING AREA

The switching safe operating area (SOA) of Figure 8 is the

boundary that the load line may traverse without incurring

damage to the MOSFET. The fundamental limits are the

peak current, I

and the breakdown voltage, V

(BR)DSS

. The

switching SOA shown in Figure 8 is applicable for both turn–

on and turn–off of the devices for switching times less than

one microsecond.

The power averaged over a complete switching cycle must

be less than:

J(max)

– T

θJC

Figure 9. Thermal Response

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

θJC

(t) = r(t) R

θJC

= 1.67°C/W MAX

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t

J(pk)

– T

= P

(pk)

θJC

(t)

(pk)

DUTY CYCLE, D = t

t, TIME (ms)

0.01

D = 0.5

0.05

0.01

SINGLE PULSE

0.01

0.02

0.03

0.02

0.05

0.1

0.2

0.3

0.5

0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000

0.1

0.2

4–817

Motorola TMOS Power MOSFET Transistor Device Data

, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Figure 10. Capacitance Variation

1600

4030

1200

800

400

100

= 25°C

= 0

f = 1 MHz

oss

iss

rss

0 5 10 15 20 25 30 35 40 45 50

, TOTAL GATE CHARGE (nC)

Figure 11. Gate Charge versus

Gate–To–Source Voltage

= 25°C

= 12 A

= 30 V

80 V

50 V

, GATE SOURCE VOLTAGE (VOLTS)

–2

–4

–6

–8

–10

–12

–14

–16

RESISTIVE SWITCHING

PULSE GENERATOR

out

gen

50 Ω

z = 50 Ω

50 Ω

DUT

Figure 12. Switching Test Circuit

off

OUTPUT, V

out

d(off)

d(on)

90%90%

10%

INPUT, V

10%

50%

90%

50%

PULSE WIDTH

Figure 13. Switching Waveforms

INVERTED