Handbook
издательство: ESA-ESTEC Data Systems Division / Microelectronics Section Noordwijk, The Netherlands 2 December 2011
225 стр. Содержание: Radiation environment and integrated circuits
- Radiation sources (Solar flares, Coronal mass ejections, Solar wind, Galactic cosmic rays)
- Radiation environment (Van Allen belts, Atmospheric neutrons, Terrestrial radiation sources)
- The different types of interactions
- Radiation effects (Cumulative effects, Single Event Effects (SEEs) )
- Choosing a design hardening strategy
Technology selection and process level mitigation
- Mitigation techniques (Epitaxial layers, Silicon On Insulator, Triple wells, Buried layers, Dry thermal oxidation, Implantation into oxides)
- Technology scaling and radiation effects
Layout
- Mitigation techniques (Enclosed Layout Transistor, Contacts and guard rings)
- Radiation-hardened libraries (ESA Design Against Radiation Effects library, CERN 0.24 µm radiation hardened library, BAE 0.15 µm radiation hardened library, Ramon Chips 0.18 µm and 0.13 µm radiation hardened libraries, Aeroflex 600, 250, 130 and 90 nm radiation hardened libraries, Atmel MH1RT 0.35 µm and ATC18RHA 0.18 µm CMOS radiation hardened libraries, ATK 0.35 µm radiation hardened cell library, ST Microelectronics radiation hardened library)
Analogue circuits
- Mitigation techniques (Node Separation and Interdigitation, Analog Redundancy (Averaging), Resistive Decoupling, Filtering, Modifications in Bandwidth, Gain, Operating Speed, and Current Drive, Reduction of Window of Vulnerability, Reduction of High Impedance Nodes, Differential Design, Dual Path Hardening)
Digital circuits
- Mitigation techniques (Spatial redundancy, Temporal redundancy, Fail-Safe Finite State Machines)
- Vendor solutions (Radhard circuit manufacturers, Radhard processors, Radhard computers)
- Mixed-signal circuits Mitigation techniques (Triple Modular Redundancy)
Field Programmable Gate Arrays
- Mitigation techniques (Local Triple Modular Redundancy, Global Triple Modular Redundancy, Large grain Triple Modular Redundancy, Embedded user memory TMR, Voter insertion, Reliability-Oriented place and Route Algorithm, Temporal redundancy, Embedded processor redundancy, Scrubbing)
- Vendor solutions (Microsemi’s RTAX-S/SL antifuse-based FPGA, Aeroflex’s UT6325 antifuse-based FPGA, Microsemi’s ProASIC3/E flash-based FPGA, Atmel AT40KEL SRAM-based FPGA, Atmel ATF280F SRAM-based FPGA, Xilinx Virtex family SRAM-based FPGA (commercial grade), Xilinx Virtex-5Q SRAM-based FPGA (defense grade), Xilinx Virtex-5QV SRAM-based FPGA (space grade) )
- Device comparison for space applications
Embedded memories
- Mitigation techniques (Resistive hardening, Capacitive hardening, IBM hardened memory cell, HIT hardened memory cell, DICE hardened memory cell, NASA-Whitaker hardened memory cell, NASA-Liu hardened memory cell, Scrambling, Error Correcting Codes)
- Comparison between hardened memory cells
Embedded software
- Mitigation techniques (Redundancy at instruction level, Redundancy at task level, Redundancy at application level)
- System architecture
- Mitigation techniques (Shielding, Watchdog timers, Latching current limiters, Duplex architectures, Triple Modular Redundancy, Error Correcting Codes)
- Commercial solutions (Space Micro Proton platform, Maxwell SCS750)
- Examples of adopted architectures onboard satellites (Architecture for the MYRIADE satellite, Architecture for the REIMEI (INDEX) satellite, Architecture for the CALIPSO satellite)
Validation methods
- Real-life tests
- Ground accelerated tests (Standards and specifications, Test methodologies, Test facilities, Practical constraints, DUT preparation)
- Fault injection
- Analytical methods
издательство: ESA-ESTEC Data Systems Division / Microelectronics Section Noordwijk, The Netherlands 2 December 2011
225 стр. Содержание: Radiation environment and integrated circuits
- Radiation sources (Solar flares, Coronal mass ejections, Solar wind, Galactic cosmic rays)
- Radiation environment (Van Allen belts, Atmospheric neutrons, Terrestrial radiation sources)
- The different types of interactions
- Radiation effects (Cumulative effects, Single Event Effects (SEEs) )
- Choosing a design hardening strategy
Technology selection and process level mitigation
- Mitigation techniques (Epitaxial layers, Silicon On Insulator, Triple wells, Buried layers, Dry thermal oxidation, Implantation into oxides)
- Technology scaling and radiation effects
Layout
- Mitigation techniques (Enclosed Layout Transistor, Contacts and guard rings)
- Radiation-hardened libraries (ESA Design Against Radiation Effects library, CERN 0.24 µm radiation hardened library, BAE 0.15 µm radiation hardened library, Ramon Chips 0.18 µm and 0.13 µm radiation hardened libraries, Aeroflex 600, 250, 130 and 90 nm radiation hardened libraries, Atmel MH1RT 0.35 µm and ATC18RHA 0.18 µm CMOS radiation hardened libraries, ATK 0.35 µm radiation hardened cell library, ST Microelectronics radiation hardened library)
Analogue circuits
- Mitigation techniques (Node Separation and Interdigitation, Analog Redundancy (Averaging), Resistive Decoupling, Filtering, Modifications in Bandwidth, Gain, Operating Speed, and Current Drive, Reduction of Window of Vulnerability, Reduction of High Impedance Nodes, Differential Design, Dual Path Hardening)
Digital circuits
- Mitigation techniques (Spatial redundancy, Temporal redundancy, Fail-Safe Finite State Machines)
- Vendor solutions (Radhard circuit manufacturers, Radhard processors, Radhard computers)
- Mixed-signal circuits Mitigation techniques (Triple Modular Redundancy)
Field Programmable Gate Arrays
- Mitigation techniques (Local Triple Modular Redundancy, Global Triple Modular Redundancy, Large grain Triple Modular Redundancy, Embedded user memory TMR, Voter insertion, Reliability-Oriented place and Route Algorithm, Temporal redundancy, Embedded processor redundancy, Scrubbing)
- Vendor solutions (Microsemi’s RTAX-S/SL antifuse-based FPGA, Aeroflex’s UT6325 antifuse-based FPGA, Microsemi’s ProASIC3/E flash-based FPGA, Atmel AT40KEL SRAM-based FPGA, Atmel ATF280F SRAM-based FPGA, Xilinx Virtex family SRAM-based FPGA (commercial grade), Xilinx Virtex-5Q SRAM-based FPGA (defense grade), Xilinx Virtex-5QV SRAM-based FPGA (space grade) )
- Device comparison for space applications
Embedded memories
- Mitigation techniques (Resistive hardening, Capacitive hardening, IBM hardened memory cell, HIT hardened memory cell, DICE hardened memory cell, NASA-Whitaker hardened memory cell, NASA-Liu hardened memory cell, Scrambling, Error Correcting Codes)
- Comparison between hardened memory cells
Embedded software
- Mitigation techniques (Redundancy at instruction level, Redundancy at task level, Redundancy at application level)
- System architecture
- Mitigation techniques (Shielding, Watchdog timers, Latching current limiters, Duplex architectures, Triple Modular Redundancy, Error Correcting Codes)
- Commercial solutions (Space Micro Proton platform, Maxwell SCS750)
- Examples of adopted architectures onboard satellites (Architecture for the MYRIADE satellite, Architecture for the REIMEI (INDEX) satellite, Architecture for the CALIPSO satellite)
Validation methods
- Real-life tests
- Ground accelerated tests (Standards and specifications, Test methodologies, Test facilities, Practical constraints, DUT preparation)
- Fault injection
- Analytical methods