
then it is only necessary to scale
A
and
D
as
(AD)
+
(llp)A,
(l/p)D
0%.
128)
The gain constant associated with
H
remains invariant
under this scaling. The correctness of this procedure
follows directly from signal-flow graph concepts.
In a similar fashion, it can be shown that if the flat
gain associated with
V
is to be modified, i.e.,
H+vH
(Eq.
129)
the following capacitors must be scaled:
(B,
C,
E,
0
-+
(llvIB, (llv)C,
(llv)E,
(1lv)F
(Eq.
130)
Once satisfactory gain levels have been obtained at both
outputs, it is convenient to scale
the
admittances associ-
ated with each stage
so
that the minimum capacitor
value in the circuit becomes unity.
This
makes it easier
to observe the maximum capacitor ratios required to
realize a given circuit and also serves to “standardize”
different designs
so
that the total capacitance required
can be readily observed. The two groups of capacitors
that are to be scaled together are listed below:
Group
1:
(C,
D,
E,
G,
H,
L)
Group
2:
(A,
B,
F,
I,
J,
K)
Note that capacitors in each group are distinguished by
the fact that they are all incident
on
the same input
node of one of the operational amplifiers.
This completes the design process for synthesizing
practical SC-biquad networks.
In
the next section, a
detailed example is given to demonstrate each step of
the design.
Low-Pass
Notch
Example
The transfer function to be realized will be based on
the s-domain low-pass notch function
0.891975s’
+w;
H(s)
=
(Eq.
131)
s2
+
swp/30
+
w,”
where
wp
=
2nfjP
with
fp
=
1700
Hz.
This
transfer function provides a notch frequency off,
=
1800
Hz,
a
peak corresponding
to
a
quality factor
Qp
=
30,
and 0-dB dc gain. The assigned sampling fre-
quency is
128
kHz;
Le.,
T=
7.8125
ps.
The z-domain transfer function is conveniently
obtained via the bilinear transformation shown in Eq.
120.
Because the band-edge frequency of
1700
Hz is
much less than the sampling rate, it is not necessary to
prewarp (see Chapter
28)
H(s).
Applying the bilinear
transformation to Eq.
131
yields, after some algebraic
manipulations,
1
-
1.992202-‘
+
z-’
1
-
1.990292-’
+
0.99723~-’
H(z)
=
0.89093
(Eq.
132)
Note that in obtaining this transfer function a high
degree of numerical precision is required. However,
this does not result in high sensitivities, since the
capacitor ratios define only the departures from
-2
and
+1
in
the above terms.
Only the
HE
and
HF
realizations of the above circuit
will be given here, because they are more economical
in the number of capacitors required. The synthesis
itself is straightforward. Capacitors
C,
E
or
C,
F
are
determined from Eqs.
1?5
,Or
j2$,
respectively, and
capacitors
G,
H,
I,
J
or
G,
H,
I,
J
are
obtained from
the “simple” solutipAenApy in Table
5.
Finally, of
course,
A,
B,
D
or
A,
8,
D
are set equal to unity. The
resulting unscaled capacitor values are given in the
appropriate columns of Table
6.
Note that
in
this table
the “hats” are omitted from the F-circuit capacitors for
notational convenience.
Also
note that since
I
=
J
these
two switched capacitors
are
replaced by the
unswitched capacitor
K
(K =I
=
J)
in accordance with
Fig.
50.
As
the next step, it is appropriate to simulate the
unscaled E- and F-circuits to verify the design. The
results of the simulation will confirm the correctness
of
HE
and
HF,
in particular, that the maximum gain
in
both these realizations is approximately
10.56
dB.
However, the maximum gains for
Hk
and
HL
are very
low. To make the first stage no more susceptible to
overloads than the second stage, it is recommended
that these gains also be increased to a maximum of
10.56
dB. Specifically, it was found that
-1 1.05
dB,
HL,,max
=
-10.96
dB
Therefore, in accordance with Eq.
127,
p
=
12.0365,
fi
=
11.9124
Using these factors to rescale
A,
D
and
2,
b,
respec-
tively, as given in Eq.
128,
yields the “dynamic range
adjusted” capacitor values also shown in Table
6.
Finally, the capacitors associated with each opera-
tional-amplifier stage
are
separately rescaled
so
that
the minimum capacitor value becomes
1
pF. Table
6
shows the “final” values.
In
comparing the “final” realizations, we note that
the F-circuit requires roughly
12
times the total capac-
itance of the E-circuit, in spite of the fact that the ini-
tial values were
almost
identical.
Thus,
alternative
designs must be carried
to
completion before they can
be meaningfully compared. It should be noted that
other practical examples exist
in
which the F-circuit
designs are dramatically more efficient than the corre-
sponding E-circuit designs. The sensitivities for both
designs
are
found to be equivalent.
Other Topologies and
Comments
SC filters, as any other type of analog active filter,
consist
of
active inverting and noninverting integrators
(see Figs.
46
and
47).
It stands to reason, therefore,