Neamen D. Microelectronics: Circuit Analysis and Design

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528 Part 1 Semiconductor Devices and Basic Applications

EXERCISE PROBLEM

*Ex 7.14: Consider the common-base circuit in Figure 7.64. The transistor para-

meters are

β = 100

(on) = 0.7

=∞

= 24

pF, and

= 3

pF. (a)

Determine the upper 3 dB frequencies corresponding to the input and output por-

tions of the equivalent circuit. (b) Calculate the small-signal midband voltage

gain. (Ans. (a)

Hπ

= 223

MHz,

Hμ

= 58.3

MHz, (b)

= 0.869

)

–

10 V

–

10 V

→ ∞

= 1 kΩ

10 kΩ

100 kΩ

1 kΩ

→ ∞

–

Figure 7.64 Figure for Exercise Ex 7.14

Cascode Circuit

The cascode circuit, as shown in Figure 7.65, combines the advantages of the common-

emitter and common-base circuits. The input signal is applied to the common-emitter

circuit (Q

), and the output signal from the common emitter is fed into the common-

base circuit (Q

). The input impedance to the common-emitter circuit (Q

) is rela-

tively large, and the load resistance seen by Q

is the input impedance to the emitter

of Q

and is fairly small. The low output resistance seen by Q

reduces the Miller

multiplication factor on

μ1

and therefore extends the bandwidth of the circuit.

Figure 7.66(a) shows the high-frequency small-signal equivalent circuit. The

coupling and bypass capacitors are equivalent to short circuits, and resistance

for

is assumed to be inﬁnite.

–

Figure 7.65 Cascode circuit

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Chapter 7 Frequency Response 529

The input impedance to the emitter of Q

ie2

. From Equation (7.113) in our

previous analysis, we have

ie2



π2

1 + β







π2



(7.116)

The input portion of the small-signal equivalent circuit can be transformed to that

shown in Figure 7.66(b). The input impedance

ie2

is again shown.

The input portion of the circuit shown in Figure 7.66(b) can be transformed to

that given in Figure 7.66(c), which shows the Miller capacitance. The Miller capaci-

tance

is included in the input, and capacitance

μ1

is included in the output

portion of the Q

model. The possibility of including

in the output circuit was

discussed previously in Section 7.4.4.

In the center of this equivalent circuit,

is in parallel with

μ2

/(1 + β)

. Since

is usually large, it can be approximated as an open circuit. The Miller capacitance

is then

= C

μ1



1 + g



π2

1 + β



(7.117)

–

1 +

(c)

–

ie2

1 +

(b)

–

ie2

–

⎪⎪ R

(a)

–

Figure 7.66 (a) High-frequency equivalent circuit of cascode conﬁguration, (b) rearranged

high-frequency equivalent circuit, and (c) variation of the high-frequency circuit, including

the Miller capacitance

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530 Part 1 Semiconductor Devices and Basic Applications

Transistors Q

and Q

are biased with essentially the same current; therefore,

π1

∼

π2

and g

∼

Then

π2

= β

which yields

∼

2 C

μ1

(7.118)

Equation (7.118) shows that this cascode circuit greatly reduces the Miller multipli-

cation factor.

The time constant related to

π2

involves resistance

π2

/(1 + β)

. Since this re-

sistance is small, the time constant is small, and the corner frequency related to

π2

is very large. We can therefore neglect the effects of

μ1

and

π2

in the center por-

tion of the circuit.

The time constant for the input portion of the circuit is

Pπ

= [R

R

r

π1

](C

π1

)

(7.119(a))

where

= 2C

μ1

. The corresponding 3 dB frequency is

Hπ

2πτ

Pπ

(7.119(b))

Assuming

acts as an open circuit, the time constant of the output portion of

the circuit, from Figure 7.66, is

Pμ

= [R

R

](C

μ2

)

(7.120(a))

and the corresponding corner frequency is

Hμ

2πτ

Pμ

(7.120(b))

To determine the midband voltage gain we assume that all capacitances in the

circuit in Figure 7.66(c) are open circuits. The output voltage is then

=−g

π2

R

)

(7.121)

and

π2

= g

π1







π2

1 + β



(7.122)

We can neglect the effect of

compared to

π2

/(1 + β)

. Also, since

π2

= β

Equation (7.122) becomes

π2

∼

π1

(7.123)

and, from the input portion of the circuit,

π1

r

π1

r

π1

+ R

× V

(7.124)

Finally, combining equations, we ﬁnd the midband voltage gain is

=−g

R

)



r

π1

r

π1

+ R



(7.125)

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Chapter 7 Frequency Response 531

If we compare Equation (7.125) to Equation (7.110) for the common-emitter circuit,

we see that the expression for the midband gain of the cascode circuit is identical to

that of the common-emitter circuit. The cascode circuit achieves a relatively large

voltage gain, while extending the bandwidth.

EXAMPLE 7.15

Objective: Determine the 3 dB frequencies and midband gain of a cascode circuit.

For the circuit in Figure 7.65, the parameters are:

= 10

−

=−10

= 0.1



= 42.5



= 20.5



= 28.3



= 5.4



= 10



, and

= 0

. The transistor parameters are:

β = 150

(on) =

0.7 V,

=∞

= 35

pF, and

= 4

pF.

Solution: Since

is large for each transistor, the quiescent collector current is es-

sentially the same in each transistor and is

= 1.02

mA. The small-signal para-

meters are:

π1

= r

π2

≡ r

= 3.82 k

and

= g

≡ g

= 39.2

mA/V.

From Equation (7.119(a)), the time constant related to the input portion of the

circuit is

Pπ

= [R

R

r

π1

](C

π1

)

Since

= R

R

and

= 2C

μ1

, then

Pπ

= [(0.1)20.528.33.82] × 10

[35 + 2(4)] ×10

−12

⇒ 4.16 ns

The corresponding 3 dB frequency is

Hπ

2πτ

Pπ

2π(4.16 ×10

−9

)

⇒ 38.3 MHz

From Equation (7.120(a)), the time constant of the output portion of the circuit is

Pμ

= [R

R

μ2

= [510] ×10

(4 × 10

−12

) ⇒ 13.3ns

and the corresponding 3 dB frequency is

Hμ

2πτ

Pμ

2π(13.3 ×10

−9

)

⇒ 12 MHz

From Equation (7.125), the midband voltage gain is

= g

R

)



r

π1

r

π1

+ R



= (39.2)(510)



(20.528.33.82)

(20.528.33.82) + (0.1)



= 126

Comment: As was the case for the common-base circuit, the 3 dB frequency for the

cascode circuit is determined by capacitance

in the output stage. The bandwidth

of the cascode circuit is 12 Mz, compared to approximately 3 MHz for the common-

emitter circuit. The midband voltage gains for the two circuits are essentially the

same.

Computer Veriﬁcation: Figure 7.67 shows the results of a PSpice analysis of the

cascode circuit. From the hand analysis, the two corner frequencies are 12 Mz and

38.3 MHz. Since these frequencies are fairly close, we expect the actual response to

show the effects of both capacitances. This hypothesis is veriﬁed and demonstrated

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532 Part 1 Semiconductor Devices and Basic Applications

in the computer analysis results. The curves marked “

only” and “

“C

and

only” are fairly close together, and their slopes are steeper than

−6

dB/octave, which

shows that more than one capacitor is involved in the response. At a frequency of

12 MHz, the response curve is 3 dB below the maximum asymptotic gain, and the

midband gain is 120. These values closely agree with the hand analysis results.

The curves marked “

= 5

pF” and “

= 150

pF” show the circuit response

if the transistor is ideal and only a load capacitance is included.

EXERCISE PROBLEM

*Ex 7.15: The cascode circuit in Figure 7.65 has parameters

= 12

−

= 0

= 58.8



= 33.3



= 7.92



= 7.5



= 1



0.5 k



, and

= 2



. The transistor parameters are:

β = 100

(on) =

0.7 V,

=∞

= 24

pF, and

= 3

pF. Let

be an open circuit. (a) De-

termine the 3 dB frequencies corresponding to the input and output portions of the

equivalent circuit. (b) Calculate the small-signal midband voltage gain. (c) Corre-

late the results from parts (a) and (b) with a computer analysis. (Ans. (a)

Hπ

7.15 MHz,

Hμ

= 33.6

MHz, (b)

|=22.5

)

Emitter- and Source-Follower Circuits

In this section, we analyze the high-frequency response of the emitter follower. We

will analyze the same basic circuit conﬁguration that we have considered previously.

The results and discussions also apply to the source follower.

Figure 7.68 shows an emitter-follower circuit with the output signal at the

emitter capacitively coupled to a load. Figure 7.69(a) shows the high-frequency

small-signal equivalent circuit, with the coupling capacitors acting effectively as

short circuits.

We will rearrange the circuit so that we can gain a better insight into the circuit

behavior. We see that

is tied to ground potential and also that

is in parallel with

and

. We may deﬁne



= R

R

r

In this analysis we neglect the effect of

. Figure 7.69(b) shows a rearrangement of

the circuit.

7.6.3

f (Hz)

100

200

= 150 pF

= 5 pF

only

and C

only

Figure 7.67 PSpice analysis results for cascode circuit

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Chapter 7 Frequency Response 533

We can ﬁnd the impedance



looking into the base without capacitance

The current



entering the parallel combination of

and

is the same as that

coming out of the combination. The output voltage is then

= (I



+ g



(7.126)

–

Figure 7.68 Emitter-follower circuit

(a)

(b)

–

⎪⎪ R

–

(c)

(1 + g

' )

1 + g

–

Figure 7.69 (a) High-frequency equivalent circuit of emitter follower, (b) rearranged high-

frequency equivalent circuit, and (c) high-frequency equivalent circuit with effective input

base impedance

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534 Part 1 Semiconductor Devices and Basic Applications

Voltage

is given by



(7.127)

where

= (1/r

) + sC

Voltage

= V

+ V

Therefore,



+ V



(7.128)

Combining Equations (7.126), (7.127), and (7.128), we obtain



+ R



(7.129(a))



(1 + g



) + R



(7.129(b))

Substituting the expression for

, we ﬁnd



+sC

×(1 + g



) + R



(7.130(a))

This can then be written as



(1 + g



)

(1 + g



)

+ R



(7.130(b))

Impedance



is shown in the equivalent circuit in Figure 7.69(c). Equa-

tion (7.130(b)) shows that the effect of capacitance

is reduced in the emitter-

follower conﬁguration.

Since the emitter-follower circuit has a zero and two poles, a detailed analysis of

the circuit is very tedious. From Equations (7.126) and (7.127), we have

= V

+ g



(7.131)

which yields a zero when

+ g

= 0

. Using the deﬁnition of

, the zero occurs at

2πC



1 + β



(7.132)

Since

/(1 + β)

is small, frequency

is usually very high.

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Chapter 7 Frequency Response 535

If we make a simplifying assumption, we can determine an approximate value

of one pole. In many applications, the impedance of

(1 + g



)

in parallel with

/(1 + g



)

is large compared to



. If we neglect



, then the time constant is

= [R

R

(1 + g



]



1 + g





(7.133(a))

and the 3 dB frequency (or pole) is

2πτ

(7.133(b))

EXAMPLE 7.16

Objective: Determine the frequency of a zero and a pole in the high-frequency

response of an emitter follower.

Consider the emitter-follower circuit in Figure 7.68 with parameters

= 5

−

=−5

= 0.1



= 40



= 5.72



= 0.5



, and

10 k



. The transistor parameters are:

β = 150

(on) = 0.7

=∞

35 pF, and

= 4

pF.

Solution: As in previous examples, the dc analysis yields

= 1.02

mA. There-

fore,

= 39.2

mA/V and

= 3.82



From Equation (7.132), the zero occurs at

2πC



1 + β



2π(35 ×10

−12

)



3.82 × 10

151



⇒ 180 MHz

To determine the time constant for the high-frequency pole calculation, we

know that

1 + g



= 1 + g

R

) = 1 +(39.2)(0.510) = 19.7

and

= R

R

= 405.72 = 5k

The time constant is therefore

= [R

R

(1 + g



]



1 + g





= [(0.1)5(19.7)(3.82)] × 10



4 +

19.7



×10

−12

⇒ 0.566 ns

The 3 dB frequency (or pole) is then

2πτ

2π(0.566 ×10

−9

)

⇒ 281 MHz

Comment: The frequencies for the zero and the pole are very high and are not far

apart. This makes the calculations suspect. However, since the frequencies are high,

the emitter follower is a wide-bandwidth circuit.

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536 Part 1 Semiconductor Devices and Basic Applications

Computer Veriﬁcation: Figure 7.70 shows the results of a PSpice analysis of the

emitter follower. From the hand analysis, the 3 dB frequency is on the order of

281 MHz. However, the computer results show the 3 dB frequency to be approxi-

mately 400 MHz. We must keep in mind that at these high frequencies, distributed

parameter effects may need to be considered in the transistor to more accurately

predict the frequency response.

Also shown in the ﬁgure is the frequency response due to a 150 pF load capac-

itance. Comparing this result to the common-emitter circuit, for example, we see that

the bandwidth of the emitter-follower circuit is approximately two orders of magni-

tude larger.

High-Frequency Ampliﬁer Design

Our analysis shows that the frequency response, or the high-frequency cutoff point of

an ampliﬁer, depends on the transistor used, the circuit parameters, and the ampliﬁer

conﬁguration.

We also saw that a computer simulation is easier than a hand analysis, particu-

larly for the emitter-follower circuit. However, the parameters of the actual transistor

used in the circuit must be used in the simulation if it is to predict the circuit fre-

quency response accurately. Also, at high frequencies, additional parasitic capaci-

tances, such as the collector–substrate capacitance, may need to be included. This

was not done in our examples. Finally, in high-frequency ampliﬁers, the parasitic

capacitances of the interconnect lines between the devices in an IC may also be a

factor in the overall circuit response.

Test Your Understanding

*TYU 7.12 For the circuit in Figure 7.71, the transistor parameters are:

1 mA/V

= 0.8

λ = 0

= 2

pF, and

= 0.2

pF. Determine: (a) the

Miller capacitance, (b) the upper 3 dB frequency, and (c) the midband voltage gain.

(d) Correlate the results from parts (b) and (c) with a computer analysis. (Ans.

(a)

= 1.62

pF, (b)

= 3.38

MHz, (c)

|=4.60

)

*TYU 7.13 For the circuit in Figure 7.72, the transistor parameters are:

= 1

mA/V

λ = 0

= 0.4

pF, and

= 5

pF. Perform a computer

simulation to determine the upper 3 dB frequency and the midband small-signal

voltage gain. (Ans.

= 64.5

MHz,

|=0.127

)

7.6.4

f (Hz)

0.01

0.1

= 150 pF

only

and C

only

Figure 7.70 PSpice analysis results for emitter follower

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Chapter 7 Frequency Response 537

7.7 DESIGN APPLICATION: A TWO-STAGE

AMPLIFIER WITH COUPLING CAPACITORS

Objective: • Design a two-stage BJT ampliﬁer with coupling capaci-

tors such that the 3 dB frequencies associated with each stage are

equal.

Speciﬁcations: The ﬁrst two stages of a multistage BJT ampliﬁer are to be capaci-

tively coupled and the 3 dB frequency of each stage is to be 20 Hz.

Design Approach: The circuit conﬁguration to be designed is shown in Figure 7.73.

This circuit represents the ﬁrst two stages of a discrete multistage ampliﬁer.

Choices: Assume the BJTs have parameters

(on) = 0.7

β = 200

, and

=∞

= 20 kΩ

→ ∞

= 5 kΩ

= 150 kΩ

50 kΩ

2 kΩ

+5 V

–5 V

–

Figure 7.71 Figure for Exercise TYU 7.12

→ ∞

= 10 kΩ

= 100 kΩ

1 mA

→ ∞

2 kΩ

4 kΩ

–5 V

+5 V

–

Figure 7.72 Figure for Exercise TYU 7.13

= 5 V

55 kΩ

3.5 kΩ

1 kΩ

31 kΩ

–

Figure 7.73 Two-stage BJT ampliﬁer with coupling capacitors for design application

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