Neamen D. Microelectronics: Circuit Analysis and Design

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588 Part 1 Semiconductor Devices and Basic Applications

The maximum possible power conversion efﬁciency is then

η(max) =

(max)

⇒ 50%

(8.41)

This demonstrates that, in a standard class-A ampliﬁer, replacing the collector resis-

tor with an inductor doubles the maximum possible power conversion efﬁciency.

Transformer-Coupled Common-Emitter Ampliﬁer

The design of an inductively coupled ampliﬁer to achieve high power conversion

efﬁciency may be difﬁcult, depending on the relationship between the supply voltage

and the load resistance R

. The effective load resistance can be optimized by

using a transformer with the proper turns ratio.

Figure 8.29(a) shows a common-emitter ampliﬁer with a transformer-coupled

load in the collector circuit.

The dc and ac load lines are shown in Figure 8.29(b). If we neglect any resis-

tance in the transformer and assume that R

is small, the quiescent collector–emitter

voltage is

CEQ

∼

Assuming an ideal transformer, the currents and voltages in Figure 8.29(a) are

related by

= ai

and

= v

where a is the ratio of primary to secondary turns,

or simply the turns ratio. Dividing voltages by currents, we ﬁnd

(8.42)

The load resistance is

= v

. We can deﬁne a transformed load resistance as



= a

(8.43)

8.4.2

(a)

(b)

≈ 2V

DC load line, slope = –

AC load line, slope = –

′

→ ∞

a:1

–

Figure 8.29 (a) Transformer-coupled common-emitter ampliﬁer and (b) dc and ac load lines

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Chapter 8 Output Stages and Power Ampliﬁers 589

The turns ratio is designed to produce the maximum symmetrical swing in the output

current and voltage; therefore,



= a

(8.44)

The maximum average power delivered to the load is equal to the maximum

average power delivered to the primary of the ideal transformer, as follows:

(max) =

(8.45)

where V

and I

are the maximum possible amplitudes of the sinusoidal signals. If

we neglect the power dissipation in the bias resistors R

and R

, the average power

supplied by the V

source is

= V

and the maximum possible power conversion efﬁciency is again

η(max) = 50%

Transformer-Coupled Emitter-Follower Ampliﬁer

Since the emitter follower has a low output impedance, it is often used as the output

stage of an ampliﬁer.A transformer-coupledemitter follower is shownin Figure 8.30(a).

The dc and ac load lines are shown in Figure 8.30(b). As before, the resistance of the

transformer is assumed to be negligible.

The transformed load resistance is again



= a

. By correctly designing the

turns ratio, we can achieve the maximum symmetrical swing in the output voltage

and current.

The average power delivered to the load is

(8.46)

8.4.3

DC load line

AC load line, slope =

–

′

(a) (b)

C → ∞

a:1

–

Figure 8.30 (a) Transformer-coupled emitter-follower ampliﬁer and (b) dc and ac load lines

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590 Part 1 Semiconductor Devices and Basic Applications

where V

is the peak amplitude of the sinusoidal output voltage. The maximum peak

amplitude of the emitter voltage is V

, so that the maximum peak amplitude of the

output signal is

(max) = V

The maximum average output signal power is therefore

(max) =

(max)]

(8.47)

The maximum power conversion efﬁciency for this circuit is also 50 percent.

DESIGN EXAMPLE 8.8

Objective: Design a transformer-coupled emitter-follower ampliﬁer to deliver a

speciﬁed signal power.

Consider the circuit shown in Figure 8.30(a), with parameters

= 24

V and

= 8

. The average power delivered to the load is to be 5 W, the peak amplitude

of the signal emitter current is to be no more than 0.9I

, and that of the signal emit-

ter voltage is to be no more than 0.9V

. Let

β = 100

Solution: The average power delivered to the load is given by Equation (8.46). The

peak output voltage must therefore be





2(8)(5) = 8.94 V

and the peak output current is

8.94

= 1.12 A

Since

= 0.9 V

= aV

then

a =

0.9 V

(0.9)(24)

8.94

= 2.42

Also, since

= 0.9I

= I

then

0.9

1.12

(0.9)(2.42)

= 0.514 A

The maximum power dissipated in the transistor, for this class-A operation, is

= V

= (24)(0.514) = 12.3W

so the transistor must be capable of handling this power.

Bias resistors R

and R

are found from a dc analysis. The Thevenin equivalent

voltage is

= I

+ V

(on)

where

= R

R

and V

= [R

/(R

+ R

)] · V

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Chapter 8 Output Stages and Power Ampliﬁers 591

We also have

0.514

100

⇒ 5.14 mA

Since

< V

and

∼

5mA

, then

cannot be unduly large. How-

ever, if

is small, then the power dissipation in R

and R

becomes unacceptably

high. We choose

= 2.5

k, so that

(2.5)(24) = (5.14)(2.5) + 0.7

Therefore,

= 4.43

k and R

= 5.74 k.

Comment: The average power delivered by V

(neglecting bias resistor effects) is

= V

= 12.3W

, which means that the power conversion efﬁciency is

η = 5/12.3 ⇒ 40.7%

. The efﬁciency will always be less than the 50% maximum

value, if transistor saturation and distortion are to be minimized.

EXERCISE PROBLEM

*Ex 8.8: A transformer-coupled emitter-follower ampliﬁer is shown in Fig-

ure 8.30(a). The parameters are:

= 18

(on) = 0.7

β = 100

a = 10

and

= 8

. (a) Design R

and R

to deliver the maximum power to the load.

The input resistance seen by the

source is to be 1.5 k. (b) If the peak ampli-

tude of the emitter voltage

is limited to 0.9V

, and the peak amplitude of the

emitter current i

is limited to 0.9I

, determine the maximum amplitude of the

output signal voltage, and the average power delivered to the load. (Ans. (a) R

26.4 k, R

1.62 k (b) V

1.62 V, I

203 mA,

= 0.164 W)

Test Your Understanding

*TYU 8.7 For the inductively coupled ampliﬁer shown in Figure 8.28(a), the para-

meters are:

= 12

(on) = 0.7

= 0.1

k,

= 1.5

k, and

β = 75

(a) Design R

and R

for maximum symmetrical swing in the output current and volt-

age. (Let

= (1 +β)R

.) (b) If the peak output voltage amplitude is limited to

0.9V

, and the peak output current amplitude is limited to 0.9I

, determine the

average power delivered to the load, the average power dissipated in the transistor,

and the power conversion efﬁciency. (Ans. (a)

= 39.1

k,

= 9.43

k

(b)

= 38.9mW

= 57.1mW

η = 40.5%

)

8.5 CLASS-AB PUSH–PULL COMPLEMENTARY

OUTPUT STAGES

Objective: • Analyze several circuit conﬁgurations of class-AB power

ampliﬁers.

A class-AB output stage eliminates the crossover distortion that occurs in a class-B

circuit. In this section, we will analyze several circuits that provide a small quiescent

bias to the output transistors. Such circuits are used as the output stage of power

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592 Part 1 Semiconductor Devices and Basic Applications

ampliﬁers, as well as the output stage of operational ampliﬁers, and will be discussed

in Chapter 13.

Class-AB Output Stage with Diode Biasing

In a class-AB circuit, the V

voltage that provides the quiescent bias for the output

transistors can be established by voltage drops across diodes, as shown in Fig-

ure 8.31. A constant current I

Bias

is used to establish the required voltage across the

pair of diodes, or the diode-connected transistors, D

and D

. Since D

and D

are not

necessarily matched with Q

and Q

, the quiescent transistor currents may not be

equal to I

Bias

As the input voltage increases, the output voltage increases, causing an in-

crease in i

. This in turn produces an increase in the base current i

. Since the

increase in base current is supplied by I

Bias

, the current through D

and D

, and

hence the voltage V

, decreases slightly. Since voltage V

does not remain

constant in this circuit, the relationship between i

and i

, as given by Equa-

tion (8.35), is not precisely valid for this situation. The analysis in the previous sec-

tion must therefore be modiﬁed slightly, but the basic operation of this class-AB

circuit is the same.

8.5.1

–

Bias

–

Figure 8.31 Class-AB output stage with quiescent bias established by diodes

DESIGN EXAMPLE 8.9

Objective: Design the class-AB output stage in Figure 8.31 to meet speciﬁc design

criteria.

Assume

= 3 ×10

−14

for D

and D

= 10

−13

A for Q

and Q

, and

= β

= 75

. Let R

8 . The average power delivered to the load is to be 5 W.

The peak output voltage is to be no more than 80 percent of V

, and the minimum

value of diode current I

is to be no less than 5 mA.

Solution: The average power delivered to the load, from Equation (8.24), is

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Chapter 8 Output Stages and Power Ampliﬁers 593

Therefore,





2(8)(5) = 8.94 V

The supply voltages must then be

0.8

8.94

0.8

= 11.2V

At this peak output voltage, the emitter current of Q

is approximately equal to the

load current, or

∼

(max) =

(max)

8.94

= 1.12 A

and the base current is

1 + β

1.12

⇒ 14.7mA

For a minimum

= 5

mA, we can choose

Bias

= 20

mA. For a zero input

signal, neglecting base currents, we ﬁnd that

= 2V





= 2(0.026) ln



20 × 10

−3

3 × 10

−14



= 1.416 V

The quiescent collector currents are then

= I

/2)V

= 10

−13

1.416/2(0.026)

⇒ 67.0mA

For

= 8.94

V and

= 1.12

A, the base current is

= 14.7

mA, and

= I

Bias

−i

= 5.3mA

The new value of V

is then



= 2V





= 2(0.026) ln



5.3 × 10

−3

3 × 10

−14



= 1.347 V

The B–E voltage of Q

BEn

= V





= (0.026) ln



1.12

−13



= 0.781 V

The emitter–base voltage of Q

is then

EBp

= V



−v

BEn

= 1.347 −0.781 = 0.566 V

and

= I

EBp

= (10

−13

0.566/0.026

⇒ 0.285 mA

Comment: When the output goes positive, the current in Q

decreases signiﬁcantly,

as expected, but it does not go to zero. There is a factor of approximately 10

differ-

ence in the currents between Q

and Q

Design Pointer: If the output signal currents are large, the base currents in the

output transistors may become signiﬁcant compared to the bias current through the

diodes D

and D

. The change in the diode bias current should be minimized in order

to keep the small-signal voltage gain of the output stage close to unity.

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594 Part 1 Semiconductor Devices and Basic Applications

EXERCISE PROBLEM

Ex 8.9: The BJT class-AB output stage shown in Figure 8.31 is biased at

= 5

V and

−

=−5

V. The load resistance is

= 1



. The device para-

meters are

= 1.2 ×10

−14

A for the diodes and

= 2 ×10

−14

A for the

transistors. (a) Neglecting base currents, determine the value of

Bias

that induces

quiescent collector currents of

= 1

mA. (b) Assuming

= β

= 100

, deter-

mine

BEn

EBp

, and

for

= 1.2

V. (c) Repeat part (b) for

= 3 V

(Ans. (a)

Bias

= 0.6

mA; (b)

= 1.73

mA,

= 0.547

mA,

BEn

= 0.6547

EBp

= 0.6248

= 0.5827

mA; (c)

= 3.24

mA,

= 0.276

mA,

BEn

= 0.671

EBp

= 0.607

= 0.5676

mA)

Class-AB Biasing Using the V

Multiplier

An alternative biasing scheme, which provides more ﬂexibility in the design of the

output stage, is shown in Figure 8.32. The bias circuit that provides voltage V

con-

sists of transistor Q

and resistors R

and R

, biased by a constant-current source I

Bias

If we neglect the base current in Q

, then

BE1

(8.48)

and voltage

= I

+ R

) = V

BE1



1 +



(8.49)

Since voltage V

is a multiplication of the junction voltage V

BE1

, the circuit is called

a V

multiplier. The multiplication factor can be designed to yield the required

value of

8.5.2

–

Bias

–

Figure 8.32 Class-AB output stage with V

multiplier bias circuit

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Chapter 8 Output Stages and Power Ampliﬁers 595

A fraction of the constant current I

Bias

ﬂows through Q

, so that

BE1

= V





(8.50)

Also, the quiescent bias currents i

and i

are normally small; therefore, we can

neglect

and

. Current

Bias

divides between I

and I

, satisfying both Equa-

tions (8.48) and (8 50).

increases,

becomes positive, and

and

increase, which reduces

the collector current in Q

. However, the logarithmic dependence of I

, shown in

Equation (8.50), means that

BE1

and, in turn

remain essentially constant as the

output voltage changes.

DESIGN EXAMPLE 8.10

Objective: Design a Class-AB output stage using the

multiplier circuit to meet

a speciﬁed total harmonic distortion.

Assume the circuit in Figure 8.32, biased at

= 15

V and

−

=−15 V

, is the

output stage of an audio ampliﬁer that is to drive another power ampliﬁer whose

input resistance is 1 k. The maximum peak sinusoidal output voltage is to be 10 V

and the total harmonic distortion is to be less than 0.1 percent.

Solution: Standard 2N3904 and 2N3906 transistors are to be used. From the results

of Example 8.6, the THD is a function of the output transistor quiescent currents. For

the basic circuit in Figure 8.24, the THD is found to be 0.097 percent for

1.346

V, quiescent collector currents of 0.88 mA, and a peak sinusoidal output volt-

age of 10 V.

Figure 8.33 is the PSpice circuit schematic. For a peak output voltage of 10 V,

the peak load current is 10 mA. Assuming

∼

100

, the peak base current is 0.1 mA.

–

2N3904

2N3906

3.48 kΩ

–

15 V

1 mA

–

–15 V

1 k

3.25 kΩ

Figure 8.33 PSpice circuit schematic for Example 8.10

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596 Part 1 Semiconductor Devices and Basic Applications

A bias current of 1 mA is chosen to bias the

multiplier. The peak 0.1 mA

base current, then, will not greatly disturb the current through the multiplier

circuit.

We may select

= 0.2

mA (current through R

and R

) and

= 0.8

mA. We

then have

+ R

1.346

0.2

= 6.73 k

For the 2N3904, we ﬁnd that

∼

0.65 V

for a quiescent collector current of

approximately 0.8 mA. Therefore

BE3

0.65

0.2

= 3.25 k

so that

= 3.48

k.

From the PSpice results, we ﬁnd that the voltage at the base of Q

to be

0.6895 V and the voltage at the base of Q

to be

−0.6961 V

, which means that

1.3856

V. This voltage is slightly greater than the design value of

= 1.346

Listed below are the quiescent transistor parameters. The quiescent collector

currents of the output transistors are 1.88 mA, approximately twice the design value

of 0.88 mA. The total harmonic distortion is 0.0356 percent, which is well within

the design speciﬁcation.

NAME Q_Q1 Q_Q2 Q_Q3 Q_Q4

MODEL Q2N3904 Q2N3906 Q2N3904 Q2N3906

IB 1.12E-05 -5.96E-06 6.01E-06 -3.20E-06

IC 1.88E-03 -1.88E-03 7.80E-04 -9.92E-04

VBE 6.78E-01 -7.08E-01 6.59E-01 -6.92E-01

VBC -1.43E+01 1.43E+01 -7.27E-01 1.36E+01

VCE 1.50E+01 -1.50E+01 1.39E+00 -1.43E+01

BETADC 1.67E+02 3.15E+02 1.30E+02 3.10E+02

GM 7.11E-02 7.15E-02 2.98E-02 3.80E-02

RPI 2.66E+03 4.34E+03 5.01E+03 8.09E+03

Comment: Since the resulting

voltage is slightly larger than the design value,

the quiescent output transistor currents are approximately double the design value.

Although the THD speciﬁcation is met, the larger collector currents mean a larger

quiescent power dissipation. For this reason, the circuit may need to be redesigned

slightly to lower the quiescent currents.

Class-AB Output Stage with Input

Buffer Transistors

The output stage in Figure 8.34 is a class-AB conﬁguration composed of the com-

plementary transistor pair Q

and Q

. Resistors R

and R

and the emitter-follower

transistors Q

and Q

establish the quiescent bias required in this conﬁguration.

Resistors R

and R

, used in conjunction with short-circuit protection devices not

shown in the ﬁgure, also provide thermal stability for the output transistors. The

input signal

may be the output of a low-power ampliﬁer. Also, since this is an

emitter follower, the output voltage is approximately equal to the input voltage.

8.5.3

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Chapter 8 Output Stages and Power Ampliﬁers 597

When the input voltage

increases from zero, the base voltage of Q

increases,

and the output voltage

increases. The load current i

is positive, and the emitter

current in Q

increases to supply the load current, which causes an increase in the

base current into Q

. Since the base voltage of Q

increases, the voltage drop across

decreases, resulting in a smaller current in R

. This means that i

and i

also

decrease. As

increases, the voltage across R

increases, and i

and i

increase. A

net input current i

is then produced, to account for the reduction in i

and the

increase in i

The net input current is

= i

−i

(8.51)

Neglecting the voltage drops across R

and R

and the base currents in Q

and Q

,we

have

− V

) − V

−

(1 + β

(8.52(a))

and

−(v

+ V

)

(1 + β

(8.52(b))

where β

and β

are the current gains of the npn and pnp transistors, respectively. If

=−V

−

= V

= R

≡ R

, and

= β

≡ β

, then combining Equa-

tions (8.52(a)), (8.52(b)), and (8.51) produces

− V

−

)

(1 + β)R

−

−v

− V

)

(1 + β)R

(8.53)

–

Figure 8.34 Class-AB output stage with input buffer transistors

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