Neamen D. Microelectronics: Circuit Analysis and Design

Подождите немного. Документ загружается.

598 Part 1 Semiconductor Devices and Basic Applications

Since the voltage gain of this output stage is approximately unity, the output current is

∼

(8.54)

Using Equations (8.53) and (8.54), we ﬁnd the current gain of this output stage to be

(1 + β)R

(8.55)

With

in the numerator, this current gain should be substantial. A large current gain

is desirable, since the output stage of power ampliﬁers must provide the current

necessary to meet the power requirements.

EXAMPLE 8.11

Objective: Determine the currents and the current gain for the output stage with

input buffer transistors.

For the circuit in Figure 8.34, the parameters are:

= R

= 2

k,

= 100

,

= R

= 0

, and

=−V

−

= 15 V

. Assume all transistors are matched, with

β = 60

and

(npn) = V

(pnp) = 0.6

Solution: For

= 0

= i

∼

= i

15 − 0.6

= 7.2mA

Assuming all transistors are matched, the bias currents in Q

and Q

are also approx-

imately 7.2 mA, since the base–emitter voltages of Q

and Q

are equal and those of

and Q

are equal.

Solution: For

= 10

V, the output current is approximately

∼

0.1

= 100 mA

The emitter current in Q

is essentially equal to the load current, which means that

the base current in Q

is approximately

= 100/61 = 1.64 mA

The current in R

15 − (10 +0.6)

= 2.2mA

which means that

= i

−i

= 0.56 mA

and

= i

/(1 + β) = 0.56/61 ⇒ 9.18 μA

Since Q

tends to turn off when

increases, we have

∼

10 − 0.6 −(−15)

= 12.2mA

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 598 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

Chapter 8 Output Stages and Power Ampliﬁers 599

and

= i

/(1 + β) = 12.2/61 ⇒ 200 μA

The input current is then

= i

−i

= 200 −9.18

∼

191 μA

The current gain is then

100

0.191

= 524

From Equation (8.55), the predicted current gain is

(1 + β)R

(61)(2)

2(0.1)

= 610

Comment: Since the current gain determined from Equation (8.55) neglects

base currents in Q

and Q

, the actual current gain is less than the predicted value, as

expected. The input current of 191 μA can easily be supplied by a low-power

ampliﬁer.

EXERCISE PROBLEM

Ex 8.11: Consider the class-AB output stage in Figure 8.34. The parameters are:

=−V

−

= 12 V

= R

= 250

,

= 8

, and

= R

= 0

. Assume

all transistors are matched, with

β = 40

and

(npn) = V

(pnp) = 0.7

(a) For

= 0

, determine i

, i

, and i

. (b) For

= 5

V, ﬁnd i

, i

, and i

. (c) Using the results of part (b), determine the current gain of the output

stage. Compare this value to that found using Equation (8.55). (Ans. (a)

= 44.1

mA,

= i

= 1.08

mA (b)

= 0.625

= 10.0

mA,

= 0.244

mA,

= 65.2

mA,

= 1.59

mA,

= 1.35

mA (c)

= 463

from Equation (8.55) A

= 641)

Class-AB Output Stage Utilizing

the Darlington Conﬁguration

The complementary push–pull output stage uses npn and pnp bipolar transistors.

Usually in IC design, the pnp transistors are fabricated as lateral devices with low β

values that are typically in the range of 5 to 10, and the npn transistors are fabricated

as vertical devices with β values on the order of 200. This means that the npn and pnp

transistors are not well matched, as we have assumed in our analyses.

Consider the two-transistor conﬁguration shown in Figure 8.35(a). Assume the

transistor current gains are β

and β

for the npn and pnp transistors, respectively. We

can write

= i

= β

(8.56)

and

= (1 +β

)β

∼

(8.57)

8.5.4

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 599 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

600 Part 1 Semiconductor Devices and Basic Applications

Terminal 1 acts as the base of the composite three-terminal device, terminal 2 acts as

the collector, and terminal 3 is the emitter. The current gain of the device is then

approximately β

. The equivalent circuit is shown in Figure 8.35(b). We can use

the two-transistor conﬁguration in Figure 8.35(a) as a single equivalent pnp transistor

with a current gain on the same order of magnitude as that of an npn device.

In Figure 8.36, the output stage uses Darlington pairs to provide the necessary

current gain. Transistors Q

and Q

constitute the npn Darlington emitter-follower

that sources current to the load. Transistors Q

, Q

, and Q

constitute a composite pnp

Darlington emitter follower that sinks current from the load. The three diodes D

, D

and D

establish the quiescent bias for the output transistors.

The effective current gain of the three-transistor conﬁguration Q

–Q

essentially the product of the three individual gains. With the low current gain of the

pnp device Q

, the overall current gain of the Q

–Q

conﬁguration is similar to

that of the Q

–Q

pair.

–

Bias

–

Figure 8.36 Class-AB output stage with Darlington pairs

= i

(a) (b)

≅ b

Figure 8.35 (a) A two-transistor conﬁguration of an equivalent pnp transistor; (b) the

equivalent pnp transistor

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 600 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

Chapter 8 Output Stages and Power Ampliﬁers 601

Test Your Understanding

TYU 8.8 Consider the class-AB output stage shown in Figure 8.37. The transistor pa-

rameters are

= 100

and

= 5 ×10

−16

A for the npn device, and

= 100

and

= 8 ×10

−16

A for the pnp device. (a) What value of

will establish quiescent

collector currents of

= 1

mA with

= 0

. (b) What are the values of

BEn

and

EBp

? (c) What must be the value of

such that

= 0

. (Ans. (a)

= 1.4606

(b)

BEn

= 0.7364

EBp

= 0.7242

V; (c)

= 6.1

mV)

TYU 8.9 From Figure 8.36, show that the overall current gain of the three-transistor

conﬁguration composed of Q

, Q

, and Q

is approximately

β = β

8.6 DESIGN APPLICATION: AN OUTPUT STAGE

USING MOSFET

Objective: • Design an output stage using power MOSFETs as the

output devices.

Speciﬁcations: The output stage conﬁguration to be designed is shown in Fig-

ure 8.38. The current I

Bias

is 5 mA and the zero output quiescent current in M

and M

is to be 0.5 mA.

Bias

= 10 V

–

= –10 V

–

Figure 8.38 Output stage for design application

–

= –3 V

–

= 3 V

Figure 8.37 Figure for

exercise TYU 8.8

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 601 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

602 Part 1 Semiconductor Devices and Basic Applications

Design Pointer: The output devices are to be MOSFETs because of their superior

power characteristics. The low output resistance of the emitter follower transistors

and Q

tends to increase switching speed of the output transistors. The voltage

drop across resistor R

provides the bias to M

and M

so that crossover distortion is

minimized.

Choices: MOSFETs with parameters

= 0.8

=−0.8V

= K

5 mA/V

, and

λ = 0

are available. BJTs with parameters

= I

= 10

−12

= I

= 2 ×10

−13

, and

β = 150

are available. Also diodes with parameters

= 5 ×10

−13

are available.

Solution: For

= 0.5

mA, the gate-to-source voltages are found from

= K

GSn

− V

)

0.5 = 5(V

GSn

−0.8)

Since the two output transistors are matched, we have

GSn

= V

SGp

= 1.116 V

If we design for I

= 2 mA, then the value of resistor R

2(1.116)

= 1.116 k

Considering the BJTs, we ﬁnd

BE1

= V

EB2

= V





= (0.026) ln



2 × 10

−3

−12



= 0.5568 V

We then have

= 2(0.5568) + 2(1.116) = 3.3456 V

Neglecting base currents, the voltages across the diodes are

= V





= (0.026) ln



5 × 10

−3

5 × 10

−13



= 0.5987 V

The voltage across the

multiplier circuit is found to be

= V

−2V

= 3.3456 −2(0.5987) = 2.1482 V

We will design the

multiplier circuit such that

= (0.9)I

Bias

and

(0.1)I

Bias

. Then

BE3

= V





= (0.026) ln



(0.9)(5 × 10

−3

)

2 × 10

−13



BE3

= 0.6198 V

We also have

BE3

0.6198

(0.1)(5 × 10

−3

)

= 1.24 k

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 602 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

Chapter 8 Output Stages and Power Ampliﬁers 603

From Equation (8.48), we have

= V

BE3



1 +



2.1482 = (0.6198)



1 +



which yields

= 2.466

, so that

= 2.466 R

= 3.06

k.

We see that

EB4

= V



Bias



= (0.026) ln



5 × 10

−3

2 × 10

−13



= 0.6225 V

Then, for

= 0

, the input voltage

must be

=−V

SGP

− V

EB2

− V

EB4

=−1.116 − 0.5568 −0.6225

=−2.295 V

Comment: The required input voltage

to yield

= 0

would be designed from

the previous stage of the ampliﬁer. In addition, the circuit required to establish the

Bias

current will be considered in Chapter 10. We may notice that, except for

Bias

all the design parameters are independent of the bias voltages

and

−

8.7 SUMMARY

• In this chapter, we analyzed and designed ampliﬁers and output stages capable

of delivering a substantial amount of power to a load.

• The current, voltage, and power ratings of BJTs and MOSFETs were consid-

ered, and the safe operating area for the transistors was deﬁned in terms of these

limiting parameters. The maximum power rating of a transistor is related to the

maximum allowed device temperature at which the device can operate without

being damaged.

• Several classes of power ampliﬁers were deﬁned.

• In a class-A ampliﬁer, the output transistor conducts 100 percent of the time.

The theoretical maximum power efﬁciency for a standard class-A ampliﬁer is 25

percent. This efﬁciency can be theoretically increased to 50 percent by incorpo-

rating inductors and transformers in the circuit.

• Class-B output stages are composed of complementary pairs of transistors oper-

ating in a push-pull manner. In an ideal class-B operation, each output transistor

conducts 50 percent of the time. For an idealized class-B output stage, the theo-

retical maximum power conversion efﬁciency is 78.5 percent. However, practi-

cal class-B output stages tend to suffer from crossover distortion effects when

the output is in the vicinity of zero volts.

• The class-AB output stage is similar to the class-B circuit, except that each out-

put transistor is provided with a small quiescent bias and conducts slightly more

than 50 percent of the time. The power conversion efﬁciency of this circuit is less

than that of a class-B circuit, but is substantially larger than that of the class-A

circuit. In addition, the crossover distortion is greatly reduced.

• As an application, a class-AB output stage using MOSFETs was designed.

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 603 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

604 Part 1 Semiconductor Devices and Basic Applications

CHECKPOINT

After studying this chapter, the reader should have the ability to:

✓ Describe what factors are related to the maximum transistor current and

maximum transistor voltage.

✓ Deﬁne the safe operating area of a transistor and deﬁne the power derating

curve.

✓ Deﬁne the power conversion efﬁciency of an output stage.

✓ Describe the operation of a class-A output stage.

✓ Describe the operation of an ideal class-B output stage and discuss the concept

of crossover distortion.

✓ Describe and design a class-AB output stage and discuss why crossover distor-

tion is essentially eliminated.

REVIEW QUESTIONS

1. Discuss the limiting factors for the maximum rated current and maximum rated

voltage in a BJT and MOSFET.

2. Describe the safe operating area for a transistor.

3. Why is an interdigitated structure typically used in a high-power BJT design?

4. Discuss the role of thermal resistance between various junctions in a high-power

transistor structure.

5. Deﬁne and describe the power derating curve for a transistor.

6. Deﬁne power conversion efﬁciency for an output stage.

7. Describe the operation of a class-A output stage.

8. Describe the operation of an ideal class-B output stage.

9. Discuss crossover distortion.

10. What is meant by harmonic distortion?

11. Describe the operation of a class-AB output stage and why a class-AB output

stage is important.

12. Describe the operation of a transformer-coupled class-A common-emitter

ampliﬁer.

13. Sketch a class-AB complementary BJT push–pull output stage using a V

multiplier circuit.

14. Sketch a class-AB complementary MOSFET push-pull output stage using all

MOSFETs.

15. What are the advantages of a Darlington pair conﬁguration?

16. Sketch a two-transistor conﬁguration using npn and pnp BJTs that are equivalent

to a single pnp BJT.

PROBLEMS

Section 8.2 Power Transistors

8.1 The maximum current, voltage, and power ratings of a power MOSFET are

4 A, 40 V, and 30 W, respectively. (a) Sketch and label the safe operating area

for this transistor, using linear current and voltage scales. (b) For the com-

mon-source circuit shown in Figure P8.1, determine

and sketch the load

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 604 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

Chapter 8 Output Stages and Power Ampliﬁers 605

line that produces a maximum power in the transistor for (i)

= 24

V and

(ii)

= 40

V. (c) Using the results of part (b), determine the maximum

possible drain current for (i)

= 24

V and (ii)

= 40

8.2 The common-emitter circuit in Figure P8.2 is biased at

= 24

V. The

maximum transistor power is rated at

Q,max

= 25

W. The other parame-

ters of the transistor are

β = 60

and

(

)

= 0.7

V. (a) Determine

and

such that the transistor is biased at the maximum power

point. (b) For

= 12

mV, determine the average power dissipated in the

transistor.

8.3 For the transistor in the common-emitter circuit in Figure P8.2, the parame-

ters are:

β = 80

D,max

= 10

(

sus

)

= 30

V, and

C,max

= 1.2

(a) Design the values of

and

for

= 30

V. What is maximum

power dissipated in the transistor? (b) Using the value of

in part (a), ﬁnd

C,max

and

D,max

= 5

W. (c) Calculate the maximum undistorted ac

power that can be delivered to

in parts (a) and (b) for the assumption that

≥ 0

and

0 ≤ v

≤ V

8.4 Sketch the safe operating region for a MOSFET. Label three arbitrary points

on the maximum hyperbola. Assume each of the labeled points is a Q-point

and draw a tangent load line through each point. Discuss the advantages

or disadvantages of each point relative to the maximum possible signal

amplitude.

8.5 A power MOSFET is connected in a common-source conﬁguration as

shown in Figure P8.1. The parameters are: I

D,max

4 A, V

DS,max

50 V,

D,max

35 W, V

4 V, and K

0.25 A/V

. The circuit parameters are

40 V and R

10 . (a) Sketch and label the safe operating area for

this transistor, using linear current and voltage scales. Also sketch the load

line on the same graph. (b) Calculate the power dissipated in the transistor

for V

5, 6, 7, 8, and 9 V. (c) Is there a possibility of damaging the

transistor? Explain.

D8.6 Consider the common-source circuit shown in Figure P8.6. The transistor

parameters are V

4 V and K

0.2 A/V

. (a) Design the bias circuit

such that the Q-point is in the center of the load line. (b) What is the power

dissipated in the transistor at the Q-point? (c) Determine the minimum rated

D,max

, V

DS,max

, and P

D,max

values. (d) If

= 0.5 sin ωt V

, calculate the ac

= V

sin

(V)

–

Figure P8.2

Figure P8.1

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 605 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

606 Part 1 Semiconductor Devices and Basic Applications

power delivered to R

, and determine the average power dissipated in the

transistor.

C → ∞

= 20 Ω

= 50 V

–

Figure P8.6

8.7 A particular transistor is rated for a maximum power dissipation of 60 W if

the case temperature is at 25 °C. Above 25 °C, the allowed power dissipa-

tion is reduced by 0.5W/°C. (a) Sketch the power derating curve. (b) What

is the maximum allowed junction temperature? (c) What is the value of

dev−case

8.8 A MOSFET has a rated power of 50 W and a maximum speciﬁed junction

temperature of 150 °C. The ambient is T

amb

25 °C. Find the relationship

between the actual operating power and

case−amb

8.9 For a power MOSFET,

dev−case

= 1.5

◦

C/W,

snk−amb

= 2.8

◦

C/W, and

case−snk

= 0.6

◦

C/W. The ambient temperature is

◦

. (a) If the maximum

junction temperature is limited to

j,max

= 120

◦

C, determine the maximum

allowed power dissipation. (b) Using the results of part (a), determine the

temperature of the case and heat sink.

8.10 A power BJT must dissipate 30 W of power. The maximum allowed junc-

tion temperature is

j,max

= 150

◦

C, the ambient temperature is

◦

C, and

the device-to-case thermal resistance is

dev−case

= 2.8

◦

C/W. (a) Find the

maximum permissible thermal resistance between the case and ambient.

(b) Using the results of part (a), determine the junction temperature if the

power dissipated in the transistor is 20 W.

8.11 The quiescent collector current in a BJT is

= 3

A. The maximum al-

lowed junction temperature is

j,max

= 150

◦

C and the ambient temperature

amb

= 25

◦

C. Other parameters are

snk−amb

= 3.8

◦

C/W,

case−snk

1.5

◦

C/W, and

dev−case

= 4

◦

C/W. (a) Determine the power that can be

safely dissipated in the transistor. (b) Using the results of part (a), determine

the maximum collector-emitter voltage that may be applied.

Section 8.3 Classes of Ampliﬁers

8.12 For the class-A ampliﬁer shown in Figure 8.16(a), show that the maximum

theoretical conversion efﬁciency for a symmetrical square-wave input

signal is 50 percent.

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 606 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08:

Chapter 8 Output Stages and Power Ampliﬁers 607

8.13 Consider the emitter-follower ampliﬁer shown in Figure P8.13. (a) Assuming

β  1

, show that the small-signal voltage gain can be written in the form

+ V

(b) If

= 8 

, determine the minimum collector current that produces

a small-signal voltage gain of (i)

= 0.9

, (ii)

= 0.95,

and

(iii)

= 0.9970

8.14 Consider the emitter-follower ampliﬁer shown in Figure P8.13. An average

power of 0.5 W is to be delivered to a load of

= 8 

. (a) What are the

peak values of ac output voltage and ac load current? (b) The minimum col-

lector current occurs when

reaches the maximum negative value. If the

minimum collector current is to be 10 percent of

, determine

. (Use the

results of part (a).)

8.15 Consider the emitter-follower ampliﬁer in Figure P8.13. Since the base-emitter

voltage is a function of collector current, the voltage gain changes as the col-

lector current changes. This effect results in distortion of the output signal. As-

sume

= 8 

and

= 0.25

A. Deﬁning the voltage gain as (Problem 8.13)

find the voltage gain for (a)

=+1.6

V, (b)

= 0

, and (c)

=−1.6

8.16 Consider the class-A emitter-follower circuit shown in Figure P8.16. As-

sume all transistors are matched with

(on) = 0.7

(sat) = 0.2

and

=∞

. Neglect base currents. Determine the maximum and mini-

mum values of output voltage and the corresponding input voltages for the

circuit to operate in the linear region.

R = 1 kΩ

= 5 V

–

= –5 V

= 1 kΩ

Figure P8.16

R = 1 kΩ

+5 V

–5 V

1 kΩ

Figure P8.17

–

Figure P8.13

8.17 Consider the class-A source-follower circuit shown in Figure P8.17. The

transistors are matched with parameters

= 0.5

= 12

mA/V

, and

λ = 0

. Determine the maximum and minimum values of output voltage

nea80644_ch08_559-614.qxd 06/15/2009 01:31 PM Page 607 F506 Hard disk:Desktop Folder:ALI:MHDQ134-08 Folder:MHDQ134-08: