
DISCRETE-TIME SIGNAL PROCESSING
approximately like a resistor of value
Re,
=
(TIC).
When the frequency of the clock approaches the
Nyquist limit relative to the signal bandwidth, this
approximation begins to break down, and it is neces-
sary
to consider the details of the switch phasing in
order to determine an accurate model for the perfor-
mance of the SC circuit.
As
it
became better understood that resistor replace-
ment techniques are inaccurate for switching rates near
the Nyquist limit, SC circuit designers began to char-
acterize charge transfer relationships in SC circuits
with discrete-time difference equations and to apply
the theory of discrete time systems to analyze perfor-
mance. It was learned that
if
the output voltage is sam-
pled on the “a” switch phase, then the network shown
in Fig. 32a behaves as a forward Euler integrator, the
network of Fig. 32b as a backward Euler integrator,
and that of Fig. 32c as a trapezoidal integrator. Subse-
quently, Broderson et.
al.*
showed how high quality
SC filters can be derived from the “leapfrog” active fil-
ter structure, a particular form of a doubly terminated
LC ladder, by using SC integrator replacements.
If a toggled switched capacitor, like the one used to
replace the input resistor in the trapezoidal integrator
of Fig. 32c, is used
to
replace every resistor in an arbi-
trary RC active filter, the analog structure is trans-
formed into an SC structure according to the bilinear-z
transformation discussed earlier. If each phase of the
biphase clock has period
T,
the effective sampling rate
becomes
2/T
because the toggle switched capacitor has
identical behavior on each phase.
In
MOS
transistors, there normally is a rather large
nonlinear parasitic capacitance
C,
between the bottom
plate and the substrate, as well as a considerably
smaller parasitic capacitance
Cp
between the top plate
and the substrate.
C,
can be as much as
20%
of the fab-
ricated capacitor, and is rather difficult to predict or
compensate.
Cp
is normally an order of magnitude
smaller, although its presence can disturb a sensitive
design significantly. It is important for SC circuits to
be designed with the bottom plate of all capacitors
grounded or switched between a voltage source and
ground
so
that excess charge accumulated by the para-
sitic during the charging phase is harmlessly dis-
charged to ground and does not affect the
characteristics of the circuit. It is clear that a toggled
switched capacitor cannot be made parasitic insensi-
tive in general, since the top and bottom plates must
perfom
the same function on alternate phases. Despite
efforts to compensate for parasitics in the “bilinear
switched capacitor,” it was largely rejected by IC tech-
nologists as impractical because it led to too much
uncontrolled variation in the characteristics of the final
SC circuits.
Note that the forward and backward Euler integra-
tors of Fig.
32
are insensitive with respect to both the
top plate and bottom plate parasitics. For this reason
*
Reference
5.
these types of integrators became more successful than
the bilinear integrator, and were subsequently used in
many design methods that were eventually published.
Broderson et
al.?
described a set of practical consider-
ations for
MOS
implementation of SC circuits that
became standard rules of thumb for SC circuit design-
ers:
(1)
switched capacitor “resistors” should not close
an on amp feedback path;
(2)
there should be no float-
ing nodes; (3) at least one plate of every capacitor
should be connected to a voltage source or switched
between voltage sources; and
(4)
the noninverting op
amp input should be kept at a constant voltage (usually
grounded) or switched between voltage sources.
Although these should be guidelines rather than strict
rules, they have withstood the test of time in the sense
that most IC technologists tend to reject designs that
violate these conditions. The later book by Ghausi and
Lakerf incorporated these rules into the design proce-
dure, representing a change of philosophy from the
resistor and integrator replacement techniques that
dominated earlier designs.
Switched Capacitor
Filters
for
Voice Quality
CODECs-One successful application of switched
capacitor circuit technology has been in the realization
of analog pre- and post-filters required for digital voice
transmission in modem telephone channels. The A/D
and D/A conversion, as well as some additional signal
conditioning (companding, etc.), is implemented with
an
IC
referred to as a CODEC (coder-decoder). A
sin-
gle IC contains the “transmit” filter to handle transmis-
sion in the forward direction, the “receive” filters to
handle the returned voice signal, as well as other cir-
cuits required for signal conditioning. The industry
standard for the digital sampling rate is
8
kHz, which
is designed to prevent aliasing on a
4-kHz
telephone
channel. Prior to SC circuit technology, the transmit
and receive filtering was done with an active filter that
was implemented with expensive hybrid fabrication
techniques. With switched capacitor circuit tech-
niques, the goal of integrating the transmit and receive
filters together with the CODEC, while meeting the
rather strict system specifications, became reachable.
The philosophy is
to
switch the SC filters at a veq7
high rate (usually
256
kHz) relative to the 8-kHz sam-
pling rate of the CODEC
so
that sampled data effects
in the SC circuits are negligible, and for all intents and
purposes the SC pre- and post-filters function as ana-
log filters. The transmit filter must have a low-pass
characteristic within a
0+0.01
dB
tolerance in the pass-
band up to a ripple cutoff frequency
of
3.4
kHz.
In
the
receive channel, a post-filter is required following the
D/A converter to smooth the staircase waveform that
results from
the
reconstruction process. The receive
fil-
ter is a low-pass filter with a cutoff at 3.4
kHz,
which is
essentially the same as the antialiasing transmit filter.
i.
Reference
5.
Reference
11.