Middleton W.M. (ed.) Reference Data for Engineers: Radio, Electronics, Computer and Communications
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20-30
REFERENCE
DATA
FOR ENGINEERS
~ ~~~ ~~~ ~
16-PIN
J
CERAMIC
0
785
120
0
0
755
(19
1)
16
15 14
13
12
11
10
9
0
025
(0
631
R
NOM
0
310
(7
881
0
290
(7
361
0
280
(7
111
0
245
(6
221
0
050 (1.271
NOM
SEATING PLANE
0
014
(0
3561
Ak
0
008
(0
2031
16
PLACES
-1
0
070
(1
78)
MAX
16
PLACES
0
030
(0
76)
MIN
0
023
(0
5841
0
015
(0
381)
16
PLACES
0
012
(0
304)
MIN
4
Plh SPACING
4
bw
4
PLACES
0
100
(2
541
T
P
lSee
Note
6)
Ii
11
0
130
(3
io)
MIN
4
PLACES
NOTES
A. All dimensions are shown
in
inches
(and
parenthetically
in
millinleters
for
reference
only)
B
Each
pin
centerline is located within
0
010
(0
261
of
its true longitudinal position
Inch dimensions
govern
Fig.
16.
Dual-in-line ceramic packaging
for
integrated circuits. (From
TTL Data Book,
2nd ed. Dallas, TX: Texas Instruments,
Inc.,
1916;
p.
4-4.)
is just being introduced into manufacturing, but it
promises to rapidly advance
in
applications.
Thermal Resistance
The most important system specification of an IC
package is its ability to conduct heat, since the IC dis-
sipates power in the package. The thermal properties
of
a package
are
specified as a thermal resistance.
Junction-to-ambient thermal-resistance values of dual-
in-line packaging systems
are
shown
in
Fig.
19.
This
figure
of
merit is used
to
relate the internal chip tem-
perature to the ambient system temperature.
DIGITAL INTEGRATED
CIRCUITS
Digital logic functions can be realized in many
different configurations. The traditional logic real-
ization used resistors or diodes in conjunction with a
transistor. This approach has been replaced in the
current integrated circuits by the use of active tran-
sistors mostly, since these can be realized most effi-
ciently in the technology. The logic realization is
dependent
on
the property of the transistor used and
will be categorized differently for bipolar and field-
effect transistors.
The implementation of logic-integrated circuits
requires the definition of the voltage, current, and tim-
ing
standards. These have been defined
in
Table
8.
A
very large variety of digital logic circuits spanning SSI,
MSI, LSI,
and VLSI is commercially available. The
various manufacturers' data books and applications
books should be consulted for detailed information.
Bipolar
Logic
Fam
i
I
ies
Bipolar logic functions are commercially available
as
SSI
and MSI circuits, and they are being developed
for LSI and VLSI circuits. The different families
described here are graded from the
most
popular SSI
and MSI standard logic to the more advanced families
used for LSI and VLSI.
Transistor-Transistor Logic
(TTL)*-The most
widely used logic family for SSI and MSI logic is tran-
sistor-transistor logic.
A
broad spectrum of
TTL
cir-
cuits are available that allow logic designers to
optimize all portions of a system cost effectively.
INTEGRATED
CIRCUITS
20-3
1
16-PIN
W
CERAMIC
0
006 (0.152)
0
003 (0.0761
16
LEADS
(See Note E)
BASE AND
SEATING PLANE
\
0
080
(2 03)
0
050
I1
27)
0
040
il
02)
0
020
(0
51)
--
0.350
(8.89)
0
310 (7 87)
---T
-___-_
_i---
I
0.300 (7 62)
(See
Note
D) (See
Note
B)
\
I
I
0
285
(7 24)
!3
81
1
0
350
18
891
0
310 17
87)
Falls within JEDEC MO-OO4AG Dimensions
11
9
(See
Note
C)
0
019
(0
483)
0
015
(0
381)
16
LEADS
(See
Note E)
2345678
4
__~~
0
400
110
161
0
371
I9
421
-___
0
025
(0
64)
0 010
(0
25)
4
PLACES
NOTES.
A
All dimensions are shown
in
inches (and parenthetically in millimeters for reference only). Inch dimensions govern
B. Index point
is
provided
on
cap
for
terminal identification only
C Leads are within
0
005
(0.13)
radius of true position
(T.P
]
at maximum material condition
D
This dimension determines a
zone
within which all body and lead irregularities lie
E Not applicable
for
solder-dipped leads.
F When solder-dipped leads are specified. dipped area extends from lead
tip
to wlthin
0
050
(1
271
of package body.
Fig. 17. Ceramic flat packaging for integrated circuits, (From
7TL
Data
Book,
2nd
ed.
Dallas,
TX:
Texas Instruments, Inc., 1976;
p.
4-10.)
The basic schematic of generic TTL logic
is
shown
in
Fig.
20.
This arrangement utilizes the base-emitter
diodes and collector-base diode of the multiemitter
transistor for logic and the output transistor for drive.
This is very easily realized in planar bipolar technol-
ogy. Although the basic TTL circuit consists of two
transistors, additional components are necessary to
increase circuit speed and fan-out capability (Fig.
21).
Two major classes
of
TTL
logic exist. These are called
*
Reference 17.
54XX
and
74XX
series
TTL.
The
74XX
series
is
a
limited-temperature
(0
"C
to
+70
"C)
IC,
and
the
54XX
series is a full-military-temperature
(-55
"C
to
+125
"C)
IC.
A classification by low power and high
speed in addition to the standard series exists.
An
improvement in the TTL performance is
achieved by the addition of
a
Schottky barrier diode
that permits the transistor to operate in the nonsat-
urated mode; this reduces storage time and improves
speed. Initially, the Schottky TTL was developed for
high speed. Further evolution of the Schottky technol-
ogy led to the low-power Schottky TTL family in
20-32
REFERENCE
DATA
FOR ENGINEERS
LEADLESS CERAMIC PACKAGE CASE
703
_-
CASE
703-01
NOTE
Slots
true
positioned within
0.010
(0.25
mmi
total to dirnenshons
A
and
6
at
maximum
material
condition
Fig.
18.
Leadless ceramic chip-carrier package. (From
Motorola CMOS Datu,
1978;
p. g-14.)
which Schottky diodes replace the multiemitter tran-
sistor as the input element. The Schottky TTL circuits
are shown in Fig.
22.
Table
9
defines the voltage and current standards of
various
TTL
logic families. Table
10
shows the perfor-
mance characteristics of different
TTL
families.
Emitter-Coupled
Logic (ECLbThe highest-
speed, lowest-noise bipolar logic family is emitter-
coupled logic. It is also known as current-mode logic
(CML),
since the circuit works on a current-steering
principle.
It
is designed as a nonsaturating
form
of
logic, which eliminates transistor storage time as a
speed-limiting characteristic. The typical ECL gate
shown
in
Fig.
23
comprises a differential-amplifier
input, an internal bias reference, and
an
emitter-fol-
lower output
to
restore dc levels. High-fan-out opera-
tion is possible because of the high input impedance of
IIIIIII
I
I
14
16 22
24
28
40
NUMBER
OF
PINS
Fig,
19.
Typical thermal resistance for various packages.
(From
Motorola CMOS Datu,
1978;
p. g-3.)
TABLE
8.
DEFNITIONS
OF
LOGIC
STANDARD TERMINOLOGY
Parameter Definition
Most positive power-supply voltage for a
Bias reference supply voltage
Most negative power-supply voltage for a
High
(1)
level input voltage
High
(1)
level output voltage
Input clamp voltage
Low
(0)
level input voltage
Low
(0)
level output voltage
Negative-going threshold voltage
Positive-going threshold voltage
Off-state output voltage
On-state output voltage
High
(1)
level input current
High
(1)
level output current
Low
(0)
level input current
Low
(0)
level output current
Off-state output current
Off-state (high-impedance state) output
Short-circuit output current
Supply current
circuit
circuit
current
of
three-state output
INTEGRATED CIRCUITS
20-33
n-
vcc+
Fig. 20. The basic
TTL
circuit. (From
Designing with
TTL
Integrated Circuits.
Dallas, TX: Texas Instruments, Inc.,
1971; Fig.
1-13,
p. 12.)
IN
(A)
Standard
IN
UT
UT
IN
(A)
Standard, or low-power, circuit.
(5)
Low-power.
Fig. 22. Schottky TTL circuits. (From G. D. Kraft and
W.
N.
Toy,
MinilMicro Computer Hardware Design.
Englewood
Cliffs,
NJ:
Prentice-Hall, Inc., 1979;
p.
71.)
the differential amplifier and the low output impedance
of
the emitter follower. Power-supply noise
is
virtually
eliminated by the nearly constant current drain of the
differential amplifier even
during
transition time.
The
logic-voltage standards
for
ECL
are
shown
in
Table
11.
Note that CML circuits tend to adopt TTL voltage
standards. Typical gate speed for ECL logic
ICs is
2
ns
at
100
mW
power dissipation for commercially avail-
able circuits.
Integrated Injection Logic (I’L)*-htegrated
injection logic
(12L),
also known as merged transistor
logic (MTL), is a bipolar logic comparable in density
IN
UT
-
--
..?
(5)
High-speed TTL
Fig. 21. Diagrams
of
typical implementations
of
TTL
cir-
cuits. (From
Designing with
TTL
Integrated Circuits.
Dallas,
TX: Texas Instruments, Inc., 1971; Fig. 2-1,
p.
18,
Fig. 2-3,
p.
19.)
*
Reference 18.
20-34
REFERENCE
DATA
FOR ENGINEERS
TABLE
9.
TTL VOLTAGE
AND
CURRENT STANDARDS*
Parameter
TTL
Schottky
TTL(LS)
Units
VIH
2
(rnin)
2
(min)
V
VIL
0.8
(rnax)
0.8
(max)
V
'OH
2.4
(min)
2.5-2.77
V
VOL
0.4
(max)
0.4-0.5t
V
flH
40
(max)
20
(max)
PA
IIL
-1.6
(max)
-0.36 (max)
mA
'OH
400
(min)
400
(rnin)
PA
IOL
16 (min)
4-87
mA
*
Vcc
=
5Vf
10%.
7
Different specifications for the
54
and
74
series.
TABLE 10.54174 TTL TYPICAL PERFORMAXE CHARACTERISTICS
Low-Power Standard
High-speed
Schottky Low-Power Schottky
54/74L 54/14 54/74H 54174s 54/14LS
Power/Gate 1
mW
10
mW
22
mW
19
mW
2
mW
DelayIGate
33
ns
10
ns
6
ns
3
ns
7
ns
and power dissipation with dynamic
MOS
logic. It is
an
LSI-
or VLSI-caliber bipolar logic family. The basic
12L gate is shown in Fig. 24. The basic cell is made up
of a multiemitter
NPN
transistor operated
in
the
inverted mode and a lateral PNP transistor whose base
and collector are common to the collector and base of
the first transistor. For logic operation, the PNP tran-
sistor is used both as an injector of base current for the
NPN transistor
in
the same cell and as a current-source
load for an NPN transistor in an adjacent cell. The
operation of the basic cell
as
an inverter can be under-
stood as follows. When
V,,,
is high, all the current from
the
PNP
transistor is used up by
NPN
transistor T,
operating in the saturated mode, and no current is left
for the base of NPN transistor
T2.
Hence
V,,
is
low
and
V,,
is high. When
V,,
is low, the opposite situation
applies. Typical gate delays of 5
ns
per gate at 0.2
mW
have been achieved at 2-micron geometries. Many
advances based on self-aligned structures are being
made that are enhancing the performance
of
this
logic
Schottky
Transistor
Logic
(STL)*-Schottky
transistor logic, also called Schottky coupled transistor
logic (SCTL) and complementary constant current
logic
(C3L),
is a generic diode transistor logic (DTL)
implemented with Schottky logic diodes and a single
NPN switch transistor. Fig.
25
shows a three-output
STL gate. For relatively high-gain transistors
(hfe
>
10)
family.
DIFFERENTIAL BIAS EMITTER
AMPLIFIER NETWORK FOLLOWER
Vcc
=
GND
P
OUTPUT OUTPUT
TYPICAL VALUES
Logical
1=
-0.9V. LogcalO=
-1.75~
For
Logical
1
Input,
NOR
Output=
-
0.90
V
OR
Output=
-
1.75V
For
Logical
0
Input,
NOR
Output=
-
1.75
V
OR
Output
=
-
0.90
V
*
Reference
19.
Fig.
23.
Diagram
of
a typical
ECL
gate. (From
Signefics
ECL
Data
Book.)
INTEGRATED CIRCUITS
20-35
TABLE
11.
LOGIC
STANDARDS
FOR
10
000
SERIES
ECL”
10 100 10 500
Parameter
10 200
10
600
V,
bin)
-1.85
V
-1.85
V
V,
(max)
4.81
V
-0.72
V
VoL
bin)
-1.85
V
-1.85
V
VoL
(max)
-1.65
V
-1.62
V
V,,
bin)
-0.96
V
-0.93
V
VoH
(ma)
4.98
V
-0.95
V
VBB
(typical)
-1.29
V
-1.29
V
*
25 “C,
VEE
=
5.2
V,
Vcc
=
ground
Fig.
24.
The integrated-injection-logic,
12L,
gate. (From
K.
Hart
and
A.
Slob,
“Integrated Injection Logic,”
IEEE
Trans.
Solid State Circuits,
SC-7 (1972),
p.
346.)
Fig.
25.
Three-output
STL
gate.
(From
K.
Hart
and
A.
Slob,
“Integrated Injection Logic,”
IEEE
Trans. Solid State Cir-
cuits,
SC-7 (1972),
p.
346.)
and fan-out limited to one per logic diode, the signal-
voltage swing is shown to be the difference in the
Schottky-diode forward voltages.
The
STL character-
istics are compatible with the supply voltages, power,
density, and speed requirements of VLSI circuits. Typ-
ical on-chip gate speeds of less than
2
ns at
10
pW
of
power are achievable with 2-micron technology.
MOS
Logic
Families*
There
are
two classes of MOS logic families, based
on the operation of the logic:
(A)
static,
or
ratioed,
*
Reference
9.
logic and (B) dynamic, or ratioless, logic. The realiza-
tion of these two classes of logic is further described by
technology
type:
p-channel (PMOS), n-channel
(NMOS),
and complementary
(CMOS).
The
unique
feature of a
MOS technology is the symmetric nature of the
MOS-
FET. This has been utilized
in
logic circuits by the use
of
a
pass transistor as shown
in
Fig.
26.
The signal flow
can be interrupted by the use of such a series switch
when the switch is turned
off.
In
the on state, the switch
allows signal flow in either direction.
Static,
or
Ratioed,
Logic-The generalized sche-
matic of a static, or ratioed, logic gate is shown in Fig.
27A. It consists of a load device and
a
driver device or
several driver devices that can be switched to perform
a
logic function. The ideal characteristic for a load device
is
a
constant-current source. The typical device realiza-
tion of the load
in
a PMOS or
NMOS
technology is
an
active depletion-type transistor with the gate and source
connected
as
shown
in
Fig. 27B. The typical load line
achieved by
this
technique is shown
in
Fig. 28. Note
that the nonideal behavior is due to the change
in
the
depletion-mode-device threshold voltage with source-
to-substrate bias, commonly known as the body effect.
This static circuit has a logic high level determined by
the power-supply voltage, since the driver device is
switched
off
in this state and only draws subthreshold
current. The logic low level is determined by the ratio
of the load current and the on current of the driver
device. This ratio is a function of the threshold and
aspect ratio of the load and the driver device defined as
the beta ratio of the inverter. This
is
the most important
design parameter for ratioed static logic.
(Width/Length),yer
(
Width/Length)load
Beta ratio
=
The load current is constantly turned
on
in this circuit
for
the depletion load realization as in PMOS or
NMOS. This causes
a
static power dissipation in one
logic state. The static logic has the advantage of being
totally asynchronous and requires
no
clock pulses. The
power dissipation is drastically reduced by the use of
CMOS
technology (Fig. 27C). The load is a p-channel
20-36
*A
Signal propagates in both directions when
4~
is high
Fig.
26.
Pass transistor
in
MOS
logic.
$-...
(A)
Generic
logic.
(Bj
PMOS
or
NMOS
reollzotion wlth
depletlon
load.
+
(C)
CMOS
Inuerter
Fig.
27.
Static, or ratioed, logic.
transistor, and the driver is an n-channel transistor. The
CMOS inverter or logic gate draws power only during
state transition. Note also that the CMOS static
inverter has an inherently large ratio since one device
is in the subthreshold regime in each state.
Dynamic,
or
Ratioless, Logic-The use
of
dynamic, or clocked, logic for MOS circuits is very
attractive for low-power synchronous applications.
Examples
of
dynamic logic gates realized in NMOS
and
CMOS
technology are shown in Fig.
29.
The use
Fig.
28.
Typical load line achieved
with
depletion load.
of two-phase clocks in synchronous systems is stan-
dard practice. The timing of these clocks is shown in
Fig.
29A.
The
$A
clock
turns
on the active load and
precharges the output node
to
the supply voltage inde-
pendent of the state of the input. The
$B
clock dis-
charges the output only if the input logic combination
is appropriate. This time-multiplexed logic is possible
if the leakage rate through the clocked transistors does
not discharge the output stage within a clock period.
This scheme requires the generation of a two-phase
clock for NMOS and PMOS circuits. However, for the
CMOS
circuit (Fig.
29B),
single-clock operation is
possible. The advantages of dynamic logic are the low
power required and synchronous operation.
It
is
assumed that the clock propagation speed on-chip is
faster than the clock period. This requirement tends to
limit the overall gate speed for a given technology.
Microprocessors and
Minicomputers*
The implementation of logic in integrated circuits
in
the decade of the
1960s
relied on providing building
blocks that integrated unique functions.
A
major
breakthrough in logic implementation was provided in
the early
1970s
by devices that controlled logic opera-
tions with a stored program. These devices made com-
plete computing systems possible with
a
minimum
number of
ICs.
A
simplified block diagram of a micro-
computer is illustrated in Fig.
30.
The complete com-
puting system consists of inpdoutput
(I/O),
a
central
processing unit (CPU), and memory sections for the
program and data.
In
early microcomputers these ele-
ments were all separate, and in most cases each ele-
ment consisted of several different
ICs.
The function
of each
of
these sections is as follows.
I/O
section-The lines at the left
of
the
110
section
shown
in
Fig.
30
connect the computer
to
the input and
output devices, and receive instructions from the CPU.
*
References
20
and
21.
INTEGRATED CIRCUITS
20-37
VDD
1t
(A)
NMOS
or
PMOS.
VDD
P
P
-5
(BJ
CMOS.
Fig. 29. Dynamic logic
Memory
De~ces
Fig.
30.
Simplified block diagram of
a
computer system.
(From H. Corporad,
Microprocessors Architectures: From
VLIW
to
PA.
West Sussex, England: John Wiley
&
Sons,
Inc., 1998.)
A simplified diagram
of
a typical
I/O
section is shown
in
Fig.
31.
Input and output multiplexers (MPX or
MUX),
also known as data selectors, perform selection
of the
1/0
devices. Output information is stored
in
the
output buffers. The
1/0
register provides temporary
storage during the transmission of information between
the CPU and
1/0
sections.
CPU-The heart of this type
of
computer is the cen-
tral processing unit, usually called the CPU. The CPU
is the part of the computer that controls all the other
parts. Designs vary widely but, in general, the CPU
consists of the control unit, the arithmetic and logic
unit
(ALU)
and memory (registers, cache,
RAM
and
ROM)
as well as various temporary buffers and other
logic. The control unit fetches instructions from mem-
ory and decodes them to produce signals that control
the other parts
of
the computer. This may cause
it
to
transfer data between memory and ALU or to activate
peripherals to perform input or output. A parallel com-
puter has several CPUs that may share other resources
such as memory and peripherals. The term “processor”
is sometimes used
in
place of “CPU.” Fig.
32
shows a
Fb
Tofirom
CPU
Registers
Input
*
Devices
2
Buffers Multiplexer
Fig. 3
1.
Typical I/O section. (From
R.
Henle and
B.
Kuvshi-
noff,
Desktop Computers.
New York Oxford University
Press, Inc., 1992.)
To/From
Accumulator
I,(j-~l
t
Register
Control
1
Unit
I
Fig. 32. The CPU. (From
R.
Henle and
B.
Kuvshinoff,
Desk-
top Computers.
New York Oxford University Press, Inc.,
1992.)
block diagram of the components of a very simple
CPU. The connection between the arithmetic logic unit
(ALU) and the accumulator and other registers deter-
mines the number of bits that the ALU can process in
parallel. This is called the word length of the CPU.
Word lengths of
32
and 64 bits are not uncommon. The
ALU performs arithmetic operations, such
as
addition
and subtraction, and logic operations, such
as
detec-
tion of equality. The CPU uses several registers as data
registers, working registers, and scratch pad memory
(A and
B);
these help in storing intermediate results
and communicating with the I/O section and memory
sections (M). A specific register
(P)
acts
as
the pro-
gram counter and determines the operation sequence
for the system. The program counter gives specific
sequence instructions
as
it
steps up during execution of
the program. The control unit provides direction for
the computer operation.
Memory-There
are
two sections for memory in
a
typical computer, one for data and one for instructions
for what
to
do with the data, called the program. The
1/0
section and CPU contain several temporary storage
registers for data in the form of digital information.
The majority of the data, however, is stored in the Data
memory. The details of memory functions will be dis-
cussed in the section on memory integrated circuits.
The operations that transform the data have
to
be spec-
ified in
a
form that
is
directly “understandable” by the
CPU. This language is called machine language, and
a
program written in this language is stored in the Pro-
gram memory. When data is entered into the
CPU,
the
set of operations defined by the program is performed
on the data, and then the data is either returned to the
Data memory, transferred to the
I/O
section, or both.
Available Microprocessors-A microprocessor is
a
computer whose entire CPU is contained
on
one (or
a
small number
of)
integrated circuits. The important
characteristics of a microprocessor are the widths of its
internal and external address bus and data bus (and
instruction), its clock rate, its instruction set, and its
available memory.
The first commercial microprocessor was the Intel
4004 that appeared in
1971.
This was the CPU mem-
ber of
a
set of four integrated circuits called the MCS-4,
which was originally designed for
use
in
a
calculator
but was marketed
as
a
“programmable controller for
logic replacement.” The 4004 is referred
to
as
a
4-bit
microprocessor since it processed only 4 bits of data
at
a
time (the word length). This very short word size is
due mainly to the limitations imposed by the maxi-
mum integrated circuit density then achievable.
As integrated circuit densities increased with the
rapid development of integrated circuit manufacturing
technology, the power and performance of the micro-
processors also increased. This is reflected in the
increase
in
the CPU word size from the original 4 bits
in
1971
to 64 and even
128
bits by the end of the cen-
tury.
The smaller microprocessors have relatively sim-
ple instruction sets, e.g.,
no
floating point instructions,
but they are nevertheless suitable
as
controllers for
a
very wide range of applications such
as
car engines
and microwave ovens.
The Intel 4004 was followed with over ten genera-
tions of Intel microprocessors, with current devices
being called Pentium I11 and Pentium
IV
class devices.
Many other manufacturers of microprocessors have
also become prominent. The larger, more recent
microprocessor families have gradually acquired most
of the features of large computers. As the microproces-
sor industry has matured, several families of micropro-
cessors have evolved
into
de facto industrial standards
with multiple manufacturers and numerous “support”
chips including RAM, ROM,
1/0
controllers, etc. A
single chip microprocessor may include other compo-
nents such as memory (RAM, ROM, PROM), memory
management, caches, floating-point unit, inputloutput
ports, and timers.
In the early
1990s
the Semiconductor Industry
Association (SIA) began developing a roadmap for
integrated circuit features and characteristics. This
roadmap, now called the International Technology
Roadmap for Semiconductors (ITRS), is updated each
two years, and identifies the technological challenges
and needs facing the semiconductor industry over the
ensuing
15
years. This roadmap has been instrumental
in identifying the desired performance of integrated
circuits, particularly memories and microprocessors,
and providing a set of challenges for the research com-
munity. A sample of the
2000
JTRS
update for
expected microprocessor performance for the next sev-
eral years
is
shown in
Table 12.
TABLE
12.
MICROPROCESSOR
CHARACTERISTICS*
Year
of
Production
1999 2001 2003 2005 2008 2011 2014
On-chip
clock
(MW
1,250 1,767 2,490 3,500 6,000 10,000 13,500
Technology (microns)
0.18 0.13 0.11 0.08 0.06 0.04 0.03
Chip
size
(cm’)
1.70 1.70 2.14 2.35 4.68 5.36 6.15
Mtransistors/cm
7.0 14.0 25.6 46.7 115 284 701
*
Ref.
2000
International Roadmap
for
Semiconductors.
INTEGRATED CIRCUITS
20-39
A
sampling of available microprocessor characteris-
tics
as of the year 2000 is shown in Table 13. These
features compare well with
the
projections in Table 12.
It
is
clear from Tables 12 and 13 that the micropro-
cessors of today will be significantly overshadowed by
those of
the
future.
In
many respects, these micropro-
cessors make the one-chip microcomputer a landmark
development in computer technology because they
reduce the computer to a small, inexpensive, and easily
replaceable design component.
MEMORY
INTEGRATED
CIRCUITS*
The major advantages of semiconductor memories
are
that they can utilize the most advanced technology
and they
are
required in very large volumes in all sys-
tems
so
that they provide the economies of scale in the
learning process for the maturing of the technology in
time. The large volume of memory integrated circuits
thus acts
as
a
catalyst in
the
timely development of the
technology it uses and thereby allows increases in
yield and decreases in unit costs, which in turn propels
an increase in volume. The progress in the density of
memories has been phenomenal because of this syner-
gism between the system pull for more memory at low
cost and the technology push via geometry scaling that
allows improved bit density, improved performance,
and decreased cost. Fig.
33
shows the actual and pro-
jected progression of memory integration vs. feature
size over a 30-year time frame. There seem to be no
fundamental physical roadblocks to prevent devices
from being produced at least down to the 25nm feature
*
Reference 22.
DRAM
Production
Level
5
01
1970
1975
1980
1985
1990
1995
2M)o
Mo5
Year
Fig. 33. DRAM density
vs
gate length
and
year. (after
lwai
et
al.,
Microrlrctronics
Enginrrring,
Vol.
28, 1995,
p.
147.)
size. The slight slowing of the growth is an indication
of the substantial technological hurdles that must
be
overcome for very small device geometries.
Semiconductor memories are classified according to
their function as read-only memories
(ROM)
or ran-
dom access memories
(RAM).
The use of serial access
memories has been attempted, but has not been
accepted due to both cost and performance limitations.
Memories are also classified as static and dynamic.
The static memories are able to hold data as long as
power is applied (and sometimes even without power),
while dynamic memories need to have each memory
element periodically refreshed to retain data. The
dynamic memories generally have smaller cell sizes,
so
are preferable for very high-density applications.
The highest density memories
are
dynamic random
access memories, called
DRAM.
Table
14
illustrates
TABLE
13.
AVAILABLE MICROPROCESSOR
FEATURES
Athlon Power
PC
Celeron Pentium
TI1
Xeon K6-Ill (K7) 750CXe
Manufacturer
Intel Intel
AMD AMD
TBM
Transistors
7,500,000 28,100,000
2
1,300,Ooo
22,000,000 NIA
CPU
Speed
(MHz)
800
1
,OM)
450
1,200 700
Technology (microns) 0.25
0.18
0.18
0.18 0.18
TABLE
14.
DRAM CHARACTERISTICS*
Year
of Production I999
2001
2003
2005
2008 201
I
2014
DRAM
size 256M
512M
IG 2G 6G
I
6G
4XG
Chip size (cm’) 1.32 1.45
1.59
I
.74 2.05
1.91
2.68
Technology (microns) 0.18 0.15 0.12 0.10
0.06
0.04
0.03
Gbitslcm
’
0.2
0.42 0.68
I
.46 2.97 8.99 18.1
*
Ref.
2OOO
Intrrnational Roadmap
for
Semicondiic.tor,s.