Middleton W.M. (ed.) Reference Data for Engineers: Radio, Electronics, Computer and Communications
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WET
OXIDATION
TIME
IN
MINUTES
Fig.
72.
Oxide thickness
vs
wet
RTO
time at
950
"C
and
600
torr. The oxidations were performed using
1
slm
(standard
litre
per
minute)
of
0,
and
1
slm
of
H,
to the pyrogenic steam generator.
These data indicate that the devices with
in
situ germane
cleaning (prior to polysilicon RTCVD) have breakdown
distribution comparable to that for other devices without
germane cleaning. The use of germane cleaning ensures
MOS
process reproducibility and repeatable gate pat-
terning by removing the oxide
from
the original
a&/
polysilicon interface. The devices with gate polysilicon
deposited at various temperatures (590, 620, and 650
"C)
also
show comparable breakdown characteristics.
The low-field breakdowns
in
Fig.
74
could be mostly
attributed to particles.
The
breakdown distribution data
in
Fig.
75
are for split-deposition gate devices with vari-
ous
methods
of
gate formation. These include RTCVD
(silane versus disilane chemistry) and furnace (silane
chemistry) a-Si processes, and RTCVD (silane versus
disilane chemistry) polysilicon processes at various
temperatures. The breakdown distributions are nearly
comparable and indicate acceptable characteristics for
silicon RTCVD.
RTP has also been employed
to
form silicided shal-
low source/drain junctions with low leakage current
densities (as low as
5
nA/cm2).* The buried-channel
PMOS
version of the integrated sub-0.50 pm CMOS
flow
employs nonsalicide source/drain junctions with
silicided contacts whereas the surface-channel
PMOS/
NMOS version consists of salicided structures. Figs.
76
and
77
show the sheet resistance values
of
RTP-
reacted titanium layers over doped (p+ and n+) silicon
and silicon dioxide, respectively. The RTP react pro-
cesses were performed in
1
torr nitrogen using various
one-step and two-step processes. For an initial tita-
nium layer thickness of 400
A,
the two-step processes
result in TiNEiSi, sheet resistance values of less than
4
Wsq.
on
n'p
(ASP
doped) and p'n junctions. For
800
8,
starting titanium on oxide, the RTP react pro-
cess results in a relatively oxygen-free TiN layer with
*
Reference
50.
INTEGRATED CIRCUITS
20-81
“I I
I I I
0.00
0.5
1.0
1.5
2.0
H2-T0-02
FLOW
RATIO
Fig.
73.
Effect
of
hydrogen-to-oxygen
flow
ratio
on
wet oxide thickness
for
950
“C/5
min
oxidations at
600
torr total pressure.
sheet resistance values on the order
of
20
CI/sq.
The
first RTCVD tungsten metal layer is deposited over the
RTP-reacted layer (TiN over the interlevel oxide
dielectric and TiNRiSi, in the contact holes).
Suitable tungsten RTCVD processes have been
developed for a double-level metal system for the sub-
0.50
pm CMOS technology. For the first metal level,
RTCVD tungsten is used to fill the contact holes and
form
the metal lines over TiN (using the same deposi-
tion step).
Single-Wafer Surface Cleaning
Many steps in the processing of silicon devices are
preceded by a “clean” to remove trace surface contam-
inants or to chemically pretreat the wafer surface. Tra-
ditionally, such cleans have been based nearly entirely
on chemical solutions,“ which selectively attack and
remove the surface contaminants.
A
number of factors
render these “wet” cleans increasingly undesirable.
The chemical wastes generated by such processes are
hazardous to the environment, and their proper treat-
ment and disposal are expensive. Besides
the
environ-
mental and economic concerns, stringent requirements
on device performance also dictate a trend to integrate
the
processing steps with the corresponding precleans,
so
that exposure to uncontrolled ambient can be mini-
mized. Equipment and process incompatibility has
prevented such integration involving the wet cleans.
Alternative cleans based on gas-phaselvapor-phase
chemistries are more amenable to the desired process
integration. Notable examples of such “dry” cleans are
(1)
the incorporation of an
in
situ high-temperature
hydrogen and HC1 bake prior to silicon epitaxy and
(2)
slight contact sputter etch prior to the deposition
of
metal interconnections. In the remainder of this
*
Reference
60
20-82
REFERENCE
DATA
FOR ENGINEERS
8
7
6
3
2
1
20
nm
a-!
51
+
PR
+
GeH4
+
AVP
620
‘C
POLY
0
20
40
60
80
100
BREAKDOWN DISTRIBUTION
IN
PERCENT
Fig.
74.
Breakdown characteristics
for
split-deposition gate
MOS
capacitors with
80
8,
gate oxides and various polysilicon
RTCVD
processes.
The
data are
for
devices with various surface treatments between the initial amorphous silicon
and
the subsequent poly-
silicon
RTCVD
(germane cleaning, wet HF deglaze, and photoresist coat/strip).
subsection, the possible alternative dry cleans will be
discussed along the traditional classification of surface
contaminants: native/chemical oxides
of
silicon, trace
organic, and trace metallic contaminants.
Surface Cleaning in
IC
Manufacturing-The
microstructure, material purity, and electrical proper-
ties of various interfaces between different layers
(semiconductor/dielectric,
semiconductor/semiconduc-
tor, metal/semiconductor, and others) strongly influ-
ence the overall reliability and performance
characteristics of
ULSI
circuits. The critical device
interfaces include
polysilicon/single-crystal
Si (in
bipolar transistors), Si/SiO,
(in
MOS
and bipolar tran-
sistors), silicidehingle-crystal Si, and others.
As
a
result, high-performance device fabrication requires
effective preprocess and postprocess cleaning
of
the
semiconductor surfaces to remove thin native oxide
layers and other contaminants such as residual metallic
and organic impurities.
Fig.
78
shows various possible sources
of
surface
contamination and damage in device processing (rep-
resented as “causes”) and their corresponding effects
(shown as “effects”) on the semiconductor surface.
INTEGRATED CIRCUITS
20-83
MU).
FIELD
(4
c
VM
<
7)
HIGH
FIELD
NM
2
7)
23
-
19
17
AVP
SiH,
a-Si
+
AVP
650
"C
SiH,,
POLY
AVP
Si2H6
a-Si
+
AVP
650
"C
SiH,
POLY
~
AVP
Si2H6
n-Si
+
PR
+
AVP 620
"C
POLY
AVP
SiH,
a-Si
+
AVP 620 "C
SiH4
POLY
.*
FURNACE
SiH,
a-Si
+
AVP
Si2H6
POLY
FVRNACE
SiH,
a-Si
+
AVP
650
"C
SiH,
POLY
FURNACE
SiH4
a-Si
4
AVP 620
"C
SiH,
POLY
7
-
I
4
3
1
0
FURNACE SiH,
a-Si
+
HF
+
AVP
650
"C
SiH,
POLY
..
FURNACE
SiH4
a-Si
+
PR
+
AVP 620
"C
SiHq
POLY
.
__
20
40
60
80
BREAKDOWN DlSTRlBUTlON
IN
PERCENT
100
Fig. 75. Breakdown characteristics for splitdeposition gate MOS capacitors with
80
%,
gate oxides and various amorphous silicon
and
polysilicon deposition processes.
The dark bullets show definitive cause-effect correla-
tions, and the light bullets represent likely cause-effect
links.
Wet chemical treatments (e.g.,
WOH:H,O,),
atmospheric ambient exposure, low-purity process
gases, and poor process equipment base pressure can
form
thin (up to
=30
A)
native oxide layers on silicon
surfaces.* The precise thicknesses
of
these native
oxide layers depend upon the specific source; for
instance, oxides resulting from ambient exposure are
usually less than
12
A
thick,+ whereas the chemically
grown
native oxides resulting from exposure to hot
N€&OH:H,O,
may
be
as
thick
as
17
A
or more.$
Native oxide layers
are
usually detrimental to device
performance and increase device parameter spread
owing to process repeatability problems.$
A
dilute
HF
treatment is usually used
as
the last prefumace cleaning
t
References 63 and
64.
$
Reference 62.
5
Reference 65.
*
References 61 and 62.
REFERENCE
DATA
FOR
ENGINEERS
0
1
STEP
600-650
"C/2-3
rnin
1
STEP
2
STEP
1
STEP 2 STEP
111111
I
I
111
1'11
I
11 11'111'
2 STEP
600-650
"C/2-3
rnin
I
7
+750 "C/30sec
Fig. 76. Sheet resistance values
of
RTP-reacted TiN/TiSi,
layers
over
n'p
and p'n source/drain junctions
(400
A
initial titanium).
Various I-step and 2-step
RTP
react processes
were
used.
step to remove any residual native oxide layer.* Poor
processing equipment base pressure and vacuum integ-
rity can also result in oxygen incorporation and/or for-
mation of surface native oxide 1ayers.t Fig. 78 also
summarizes various possible sources of other contami-
nants in silicon device processing. For example, metal-
lic contaminants may be incorporated into a
semiconductor substrate by wet chemicals, reactive-
ion etching, photoresist processing, and ion implanta-
tion. The current semiconductor device manufacturing
environments essentially rely
on
wet cleaning tech-
niques for removal or reduction of various types of
contaminants including the metallic impurities (e.g.,
Ni, Cr, Fe,
Cu,
Zn). The wet chemical cleaning pro-
cesses used prior
to
the
gate oxidation and other high-
temperature furnace processing steps are known to
have significant effects on the device manufacturing
yield and reliability characteristics.+
Fig. 79 presents
a
list of different processing tech-
niques for removal
of
native oxide layers from semi-
*
References 66
and
67.
7
Reference
68.
$
References 62
and
69.
conductor substrate. The common procedure for
removing native oxides (and other contaminants) prior
to epitaxial silicon (or polysilicon contact) deposition
involves an ex situ aqueous cleaning (such
as
the
so-
called RCA cleaning and a final
HF
dip), followed by
an in situ high-temperature (around 900-1200
"C)
hydrogen prebake.5 However, some
UHV-CVD
epi-
taxial growth and silicon deposition techniques essen-
tially depend on the effectiveness of an ex situ
cleaning and native oxide removal process and main-
taining an atomically clean silicon surface in the
absence
of
any form of
in
situ cleaning process." A
suitable wet cleaning step is expected to remove
most
of
the native oxide and other trace contaminants, while
a
high-temperature
H,
prebake process removes resid-
ual native oxide left on the semiconductor surface
caused by ambient exposure and/or chemical cleaning.
As
shown
in
Fig.
23,
other native oxide removal pro-
cesses have been developed that operate at lower sub-
strate temperatures compared with
the
high-temperature
hydrogen bake process. The germane-assisted native
5
References 70-72.
"
References
73
and
74
20-85
1
STEP
Ti
(SO0
k
REACT ON
OXIDE
2
STEP
1
STEP
2
STEP
1
STEP
600-650 "C/1-3
min
2
STEP
600-650
"C/1-3
rnin
+750 "C/30
sec
Fig. 77. Sheet resistance values
of
RTP-reacted TiN layers over silicon dioxide
(800
A
initial titanium).
Various
1-step and 2-step
RTP react processes were used.
oxide removal process is in the low-temperature chem-
ical
dry
cleaning category.
Fig.
80
shows the effectiveness of various surface
cleaning techniques (as specified by the process
energy sources and/or cleaning chemistries) for
removal of surface contaminants (e.g., native oxides)
and other undesirable surface effects (e.g., damage,
unwanted surface passivation bonds such as Si-F). The
dark bullets represent strong cleaning action for
removal
of
the specified contaminant or undesirable
surface effect using the specified processing technique.
Moreover, the light bullets demonstrate possible clean-
ing effect for the specified linked pair
of
process tech-
nique and surface contaminant. All
the
shown
techniques can be quite effective for removal of native
oxide layers. Thermal cleaning techniques such as the
germane process may also be useful for removal of
some metallic and organic contaminants besides native
oxide layers. Another example is the
ECR
plasma sur-
face cleaning technique which has proven effective for
removal of native oxide and organic contaminants."
Low-Temperature Germane-Based Surface
Cleaning-A low-temperature
(650-750
"C)
dry
sur-
face cleaning process is described for
in
situ removal
of native oxide layers and other surface contami-
nants.? The cleaning process chemistry consists of a
mixture
of
germane (GeH,) and hydrogen (H,) gases
with very low germane-to-hydrogen flow ratio
(10-20
ppm). The germane-based surface cleaning process
can be integrated with various thin film growth and
deposition processes such as epitaxial growth, gate
dielectric formation, and polycrystalline or amorphous
silicon deposition for
MOS
and bipolar device fabrica-
tion.
The stacking fault density measurements on epitax-
ial Si films grown following the in situ germane-
assisted native oxide removal have indicated that the
two most significant cleaning process parameters are
the
substrate temperature and GeH,:H, gas flow ratio.
Substrate temperatures much below
600
OC
result
in
insufficient native oxide removal and, as a result,
higher stacking fault densities in the grown epi layers
(for the range
of
small GeH,:H, flow ratios). More-
over, temperatures in excess
of
850-900
"C
result in
increased stacking fault density
in
the grown epi lay-
ers. The latter is probably due to nucleation of germa-
nium on the silicon surface during the
m
situ cleaning
*
References 75
and
76.
$
Reference
49.
20-86
REFERENCE
DATA
FOR ENGINEERS
Fig.
78.
Sources
of
surface contaminants and damage in semiconductor device processing.
process. The germane-assisted cleaning processes
work well in the temperature range of
650-750
OC.*
For a given substrate temperature, process pressure,
and total gas flow rate, there is a critical
Ge&:H,
flow
ratio beyond which germanium can nucleate on the
surface during the cleaning process. Germanium
nucleation can be prevented by reducing the germane-
to-hydrogen flow ratio below the critical values.
As
the
total process pressure increases, the germane-to-
hydrogen flow ratio may have to be further reduced to
prevent germanium deposition or nucleation during the
in situ cleaning cycle. The experimental results have
indicated that Ge&:H, flow ratios
in
the range of
10-
20
ppm (e.g.,
12.5
ppm) work well for effective native
oxide removal processes at
5
torr and
in
the substrate
temperature range of
650-750
“C.
The germane clean-
ing process can selectively remove native oxide layers
without etching thermal oxides. This selectivity makes
the germane-based cleaning processes superior to the
fluorine-based native oxide removal techniques.
It is expected that the GeH& processes clean the
substrate surface by direct reaction of germane with
the “loose” native oxide layer. The possible oxide
reduction reactions
are
the ones that produce volatile
germanium oxide species (GeO). The presence of a
large partial pressure of hydrogen balances the clean-
ing process and prevents germanium nucleation during
the in situ cleaning process.
Native and Chemical Oxide Cleans
by
Vapor-
Phase
HF-The vapor-phase equivalent of the aque-
ous
HF has been extensively investigated.? Among the
advantages of
this
approach are low chemical con-
sumption, low particle addition, and improvements in
electrical performance as measured by a number of
parameters, such as silicide sheet resistance and thin
oxide stress endurance. More than
3OOO
wafers pro-
cessed in a four-month period using only 1 liter of
t
References 70-80.
*
Reference
77.
INTEGRATED CIRCUITS
20-87
~~
0
UHVHEATING:
-
Works for ultrathin native oxides,
-
Requires mediumhigh T's (T>750 "C).
0
REACTION WITH ADSORBED LAYERS
OF
Si
OR Ge:
-
Works for ultrathin native oxides.
0
HYDROGEN BAKE:
-
Works for ultrathin native oxides; requires high T's (T>950 "C).
0
SPUTTERING (e.g., ARGON IONS):
-
Mediumhigh T's required
to
eliminate sputter-induced surface damage.
0
SPUTTER/CHEMICAL CLEANING (e.g., Arm2 PLASMA)
0
HF/H2O OXIDE REMOVAL:
-
May have
to
eliminate the residual Si-F bonds.
0
ION-ASSISTED CHEMICAL CLEANING (e.g., ECR PLASMA)
OTHER LOW-T CHEMICAL DRY CLEANING PROCESSES
Fig.
79.
Various
types of native
oxide
removal processes
azeotropic
HF
solution resulted
in
excellent particle
performance (Fig. 81 j. Gate oxides grown after vapor-
phase HF cleaning have shown several times improve-
ment in oxide endurance under constant-current stress
compared to aqueous HF pregate cleaning."
Comparison
of
Various Native Oxide Removal
Techniques-Table 17 summarizes the overall fea-
tures of various native oxide removal processes.
Among these processes, the conventional hydrogen
prebake process requires the highest substrate temper-
ature.? Its native oxide removal selectivity with
respect to thermal oxide and silicon is good; however,
thermal oxide undercut
on
patterned substrates may be
a problem. The hydrogen prebake technique is essen-
tially a simple process and compatible with the con-
ventional epitaxial growth reactors and processes.
Sputter etch processes using RF or ECR plasmas
(Ar
or
Arm,
ambients) can also be used for native oxide
removal.$ These processes require medium substrate
temperatures,
on
the order
of
750-850
"C,
in order to
eliminate sputter-induced surface damage. The sputter
etch techniques offer poor etch selectivity with respect
to thermal oxide and silicon and are not usually com-
patible with the conventional thermal
CVD
equipment.
For in situ cleaning applications, the use of sputter etch
native oxide removal modules may be acceptable
in
vacuum-integrated cluster tools for some applications.
According
to
Table 17, the chemically enhanced
ion-assisted ECR or
RF
plasma native oxide removal
processes are effective for low-temperature (T
5
500
"Cj removal of native oxide layers without leaving any
residual surface damage.§ Hydrogen or a mixture of
hydrogen and silane have been used for chemically
enhanced plasma removal of native oxide layers.
These processes require special plasma equipment
*
Reference 49.
t
References 81-84.
$
References 76
and
85-87.
§
References 75
and
88-92.
20-88
PROCESS TECHNIQUES
PHOTOCHEMICAL
VAPOR (HF/H,O PHASE ETC) PROCESS
REMOTE PLASMA
REFERENCE
DATA
FOR ENGINEERS
CONTAMINANTS
NATIVE FLL'ORO- DAMAGED UNWANTED
OXIDE CARBONS SURFACE BONDS
METALLIC ORGANIC PARTICLES SURFACE
@@@70?@
?
?@?
om@?
?
XO
SPUTTER+CHEM SPUlTER AND ETCH
><a
\
/\
0 0
@a@
THERMAL CWNING AND
MULTIPROCESSING
(SWIM GERMAN0
ECR PLASMA
?@.00?0
HYBRID METHOD
1
ECR+DUV
HYBRID METHOD
2
Fig. 80. Effectiveness of various surface cleaning techniques for removal of native oxide layers and other surface contaminants in
semiconductor device fabrication.
ox><
?
@XXX
/\
/
00?
modules and
are
incompatible with standard epitaxial
growth
or
deposition equipment. Remote plasma-
enhanced processes such as those with remote hydro-
gen plasma can remove thin native oxide layers at
relatively low temperatures
(15O-5OO
"C).*
These pro-
cesses require special plasma modules and are rather
ineffective for removal of thicker (e.g., over
10-15
A)
native oxides. They may also generate particles if a
quartz discharge tube is used.
As
shown
in Table
17,
the low-temperature thermal
native oxide removal processes based on the fluorine-
containing gases (e.g.,
NF,
or
CIF,)
require special
corrosion-resistant equipment and offer rather poor
native oxide etch selectivity with respect
to
thermal
oxide and si1icon.t Another potential problem with
these processes is the possibility of formation
of
Si-F
surface passivation bonds and/or residual chlorine
remaining on the surface. Special care is needed to
prevent surface etch pits. Substrate heating in a UHV
environment such
as
in an
MBE
chamber can remove
thin native oxide layers at medium temperatures with
relatively good etch selectivity with respect to thermal
oxide and silicon;$ however, this technique requires
expensive UHV hardware and is not compatible with
the conventional silicon processing equipment. In situ
deposition
of
a submonolayer of germanium
or
silicon
on the substrate prior to a UHV heating cycle can help
to further reduce the substrate temperature required for
removal of thin native oxide layers.$
Vapor-phase removal of native oxide layers is per-
formed based on the
HF/H,O
chemistry at room tem-
perature." One advantage
of
the HF-based vapor phase
processes is the capability for providing very good
native oxide etch selectivity with respect to other
material layers including thermal oxides; however, the
HF/H,O-based vapor-phase processes cannot be per-
formed in the conventional processing equipment and
*
Reference
93.
t
References 94 and
95.
j:
References
96
and 97.
$
Reference 98.
"
References
99-101.
INTEGRATED CIRCUITS
600
500
[
400
8
4
8
2
2
300
0
z
3
200
e
100
20-89
-
-
-
-
-
-
-
-
-
-
-
-
-
0-
-
700
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
-1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
1
2
3
4
5
6
7
8
WEEK
NUMBER
Fig.
81.
Particle performance
of
aqueous
and
vapor-phase
HF
native oxide etch.
require a dedicated special process chamber.
As
shown
in Table
17,
photochemical cleaning refers to the ultra-
violet-enhanced processes for native oxide removal at
medium temperatures." These processes are excellent
candidates for low-temperature removal of metallic
and organic contaminants as well. They require special
photochemical equipment and are incompatible with
the standard thermal processing equipment. Finally, as
indicated in Table
17,
the germane-based native oxide
removal process is compatible with the conventional
silicon processing equipment. This process is effective
for native oxide removal at low to medium substrate
temperatures and provides good native oxide etch
selectivity with respect to thermal oxide layers and sil-
icon.
Organic Cleans-The removal
of
trace organic
contaminants using ozone and atomic oxygen gener-
ated by irradiating
an
oxygen containing ambient with
deep
UVt
is now firmly established as a viable substi-
tute for the traditional wet organic clean. The photoac-
tivation of oxygen and the subsequent generation of
*
References
102
and
103
5.
Reference
104.