Neamen D. Microelectronics: Circuit Analysis and Design

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Comment: We showed previously that the output resistance of an emitter-follower

circuit is low. For comparison, typical output resistance values for the 741 op-amp

are

75 

. This correlates well with our analysis.

EXERCISE PROBLEM

Ex 13.6: Repeat Example 13.6 assuming Early voltages of

= 100

V. (Ans.

= 90.9 

)

Frequency Response

The 741 op-amp is internally compensated by the Miller compensation technique to

introduce a dominant low-frequency pole. From Miller’s theorem, the effective input

capacitance of the second gain stage is

= C

(1 +

)

(13.30)

The dominant low-frequency pole is

2π R

(13.31)

where

is the equivalent resistance between the second-stage input node and

ground, and is

= R

R

(13.32)

Here R

is the input resistance of the gain stage and R

is the output resistance of the

diff-amp stage. From Figure 13.10, we see that

= R

act1

r

(13.33)

EXAMPLE 13.7

Objective: Determine the dominant-pole frequency of the 741 op-amp.

Use appropriate results from previous calculations.

Solution: Previously, we determined that

= 285

, which means that the effec-

tive input capacitance is

= C

(1 +

) = (30)(1 +285) = 8580 pF

The gain stage input resistance was found to be

= 4.07 M

. We ﬁnd

= R

act1

r

= 7.185.26 = 3.04 M

The equivalent resistance is then

= R

R

= 3.044.07 = 1.74 M

Finally, the dominant-pole frequency is

2π R

2π(1.74 ×10

)(8580 × 10

−12

)

= 10.7Hz

Comment: The very large equivalent input capacitance

justiﬁes neglecting any

other capacitance effects at the gain stage input.

13.2.4

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EXERCISE PROBLEM

Ex 13.7: Repeat Example 13.7 assuming Early voltages of

= 100

V. See

Exercise Problems Ex 13.4, Ex 13.5, and Ex 13.6. (Ans. 3.88 Hz)

If all other poles of the op-amp circuit are at very high frequencies, then the

unity-gain bandwidth is

= A

(13.34)

Using our results, we ﬁnd that

= (181,260)(10.7)

∼

1.9 MHz

(13.35)

A typical unity-gain bandwidth value for the 741 op-amp is 1 MHz. With all the

approximations and assumptions, such as the value of reverse saturation current and

Early voltage, used in the calculations, a factor of two between the actual and pre-

dicted cutoff frequency is not signiﬁcant.

If the frequencies of the other poles of the 741 op-amp are greater than 1.9 MHz,

the phase margin is 90 degrees. This phase margin ensures that any closed-loop am-

pliﬁer circuit using the 741 op-amp will be stable for any feedback transfer function.

Problem-Solving Technique: Operational Ampliﬁer Circuits

1. DC analysis. The bias portion of the op-amp circuit must be identiﬁed. A

reference current must be determined and then the bias currents in the indi-

vidual building blocks of the overall circuit can be determined.

2. AC analysis. The small-signal properties of the building blocks of the overall

circuit can be analyzed individually, provided that the loading effects of

follow-on stages are taken into account.

Test Your Understanding

TYU 13.3 Using the results of Example 13.1 and assuming

= 200

, determine the

input base currents to

and

. (Ans.

= I

= 47.5

nA)

TYU 13.4 The 741 op-amp in Figure 13.3 is biased at

= 15

V and

−

=−15

Assume

(npn) = V

(pnp) = 0.6

V. Determine the input common-mode voltage

range, neglecting voltage drops across R

and R

. (Ans.

−12.6 <v

(cm)

≤ 14.4

TYU 13.5 (a) If the 741 op-amp in Figure 13.3 is biased at

=15

and

−

=−15

estimate the maximum and minimum output voltages such that the op-amp remains

biased in its linear region. (b) Repeat part (a) if

= 5

V and

−

=−5

V. (Ans.

(a)

−13.2 ≤ v

≤ 13.8

V (b)

−3.2 ≤ v

≤ 3.8

TYU 13.6 Consider the input stage and bias circuit in Figure 13.5 with supply volt-

ages

= 5

V and

−

=−5

V. If

= 5 ×10

−15

A for each transistor, determine

REF

BE11

BE10

BE6

, and

C10

. (Ans.

REF

= 0.218

mA,

BE11

= 0.637

C10

= 14.2 μ

BE10

= 0.566

BE6

= 0.548

TYU 13.7 The power supply voltages for the 741 op-amp in Figure 13.3 are

= 10 V

and

−

=−10 V

. Neglect base currents and assume

(npn) =

(pnp) = 0.6V

. Calculate the bias currents

REF

C10

C13B

, and

C13A

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(Ans.

REF

= 0.47 mA

C10

= 17.2 μA

= 8.6 μA

C13B

= 0.353 mA

C13A

= 0.118 mA

)

*TYU 13.8 In the 741 op-amp output stage in Figure 13.3, the combination of Q

, and R

is replaced by two series diodes with

= 10

−14

A. The transistor

parameters are:

= 200

= 50

, and

= 50

V. Assume the same dc bias

currents calculated previously. Calculate the output resistance, assuming Q

is con-

ducting, producing a load current of 5 mA. (Ans. 41



)

13.3 CMOS OPERATIONAL AMPLIFIER CIRCUITS

Objective: • Describe and analyze the dc and ac characteristics of

CMOS operational ampliﬁer circuits.

The 741 bipolar op-amp is a general-purpose op-amp capable of sourcing and sink-

ing reasonably large load currents. The output stage is an emitter follower capable of

supplying the necessary load current, with a low output resistance to minimize load-

ing effects.

In contrast, most CMOS op-amps are designed for speciﬁc on-chip applications

and are only required to drive capacitive loads of a few picofarads. Most CMOS

op-amps therefore do not need a low-resistance output stage, and, if the op-amp in-

puts are not connected directly to the IC external terminals, they also do not need

electrostatic input protection devices.

In this section, we consider four designs of a CMOS op-amp. Initially we con-

sider a simple CMOS design to begin to understand the basic concepts of a CMOS

op-amp. We then analyze a three-stage CMOS op-amp with a complementary push-

pull output stage. The third CMOS op-amp is a more sophisticated design, called a

folded cascode op-amp. Finally, we consider a current-mirror CMOS op-amp. In

each case, we will do a dc analysis/design and a small-signal analysis/design.

MC14573 CMOS Operational Ampliﬁer Circuit

Circuit Description

An example of an all-CMOS op-amp is the MC14573, for which a simpliﬁed circuit

diagram is shown in Figure 13.14. The p-channel transistors M

and M

form the

input differential pair, and the n-channel transistors M

and M

form the active load.

The diff-amp input stage is biased by the current mirror M

and M

, in which the

reference current is determined by an external resistor R

set

The second stage, which is also the output stage, consists of the common-source-

connected transistor M

. Transistor M

provides the bias current for M

and acts as the

active load. An internal compensation capacitor C

is included to provide stability.

DC Analysis

Assuming transistors M

and M

are matched, the reference and input-stage bias

currents are given by

set

= I

− V

−

− V

SG5

set

(13.36)

13.3.1

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The reference current and source-to-gate voltage are also related by

set

= K

SG5

+ V

)

(13.37)

where

and

are the threshold voltage and conduction parameter of the

p-channel transistor M

EXAMPLE 13.8

Objective: Determine the dc bias currents in the MC14573 op-amp.

Assume transistor parameters of

= 0.5

V (all transistors),



= 100 μ

A/V



= 40 μ

A/V

, and circuit parameters of

= 5

−

=−5

V, and

set

= 225



Assume transistor width-to-length ratios of 6.25 for

and

, and 12.5 for all other

transistors.

Solution: For transistors

and

, the conduction parameters are:













0.04



(

12.5

)

= 0.25

mA/V

Combining Equations (13.36) and (13.37) yields the source-to-gate voltage of

(

SG5

+ V

)

− V

SG5

− V

−

set

0.25

(

SG5

−0.5

)

5 − V

SG5

−

(

−5

)

225

which yields

SG5

= 0.9022

Chapter 13 Operational Ampliﬁer Circuits 971

–

set

Figure 13.14 MC14573 CMOS op-amp equivalent circuit

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From Equation (13.36), we have

set

= I

10 − 0.9022

225

⇒ 40.4 μA

The quiescent drain currents in

and

are then also

40.4 μ

A, and the currents in

through

are

20.2 μ

Comment: The quiescent bias currents can be changed easily by changing the external

resistor R

set

. Transistors M

, M

, and M

are identical, so the currents in these three

devices are equal since the source-to-gate voltages are the same. The width-to-length

ratio of M

is twice that of M

and M

, which means the current in M

is twice that in

and M

. However, this is consistent with the current-source transistor currents.

EXERCISE PROBLEM

Ex 13.8: Repeat Example 13.8 assuming transistor width-to-length ratios of

(W/L)

3,4

= 10

for transistors

and

, and

W/L = 20

for all other transistors.

Let

set

= 150 k

. (Ans.

REF

= I

= 60.74 μ A, I

− I

30.37 μ

Small-Signal Analysis

The small-signal differential voltage gain of the input stage can be written as

= g

(



)

= 2



DQ1

(



)



(



)

(13.38)

where r

and r

are the output resistances of M

and M

, respectively. The input

impedance to the second stage is essentially inﬁnite; therefore, there is no loading

effect due to the second stage. If we assume that the parameter

is the same for all

transistors, then

= r

λI

(13.39)

where I

, which is the quiescent drain current in M

and M

, is

= I

The magnitude of the gain of the second stage is

= g

(

r

)

(13.40)

where

= 2



and

= r

= 1/λI

Equation (13.40) implies that there is no loading effect due to an external load con-

nected at the output.

EXAMPLE 13.9

Objective: Determine the small-signal voltage gains of the input and second stages,

and the overall voltage gain, of the MC14573 op-amp.

Assume the same transistor and circuit parameters as in Example 13.8. Let

λ = 0.02 V

−1

for all transistors.

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Solution: The conduction parameters of

and

are

= K











0.04



(

12.5

)

= 0.25

mA/V

and the output resistances are

= r

λI

(0.02)(0.0202)

⇒ 2.475 M 

From Equation (13.38), the differential voltage gain of the input stage is then



(



)

√

(

0.25

)(

0.0404

)

(2475



2475)

= 176

The transconductance of

= 2











= 2





0.1



(

12.5

)(

0.0404

)

= 0.3178

mA/V

and the output resistances of

and

are

= r

λI

(0.02)(0.0404)

⇒ 1.238 M 

From Equation (13.40), the magnitude of the voltage gain of the second stage is then

= g

(



)

(

0.3178

)(

1238



1238

)

= 197

Finally, the overall voltage gain magnitude of the op-amp is

= A

= (176)(197) = 34,672

Comment: The calculated overall voltage gain is 91 dB, which correlates very well

with typical values of 90 dB, as listed in the data sheet for the MC14573 op-amp. The

open-loop gain of a CMOS op-amp is generally less than that of a bipolar op-amp,

but the use of active loads provides acceptable results.

EXERCISE PROBLEM

Ex 13.9: Repeat Example 13.9 using circuit and transistor parameters given in

Exercise Ex 13.8. (Ans.

= 181.4

= 202.9

= 91.3

dB)

Three-Stage CMOS Operational Ampliﬁer

Figure 13.15 shows a three-stage CMOS op-amp circuit. The differential input stage

consists of the differential pair M

and M

with active load transistors M

and M

. The

input stage is biased with the constant-current source M

and M

. As shown in Chap-

ter 10, the reference current can be established with additional NMOS transistors.

The output of the input stage is connected to the common-source ampliﬁer con-

sisting of M

. The transistor M

establishes the bias current I

and also acts as the

active load for the common-source ampliﬁer.

13.3.2

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Transistors M

and M

form the complementary push–pull output stage. Tran-

sistor M

acts as a resistor and provides a potential difference between the gates of

the output transistors to minimize crossover distortion in the output signal.

Example width-to-length ratios of the transistors in the CMOS op-amp circuit

are shown in the ﬁgure. These ratios will be used in the following example.

EXAMPLE 13.10

Objective: Determine the dc and ac characteristics of a three-stage CMOS op-amp.

Consider the three-stage CMOS op-amp shown in Figure 13.15. The NMOS

transistor parameters are

= 0.7



= 80 μA/V

= 0.01 V

−1

, and the

PMOS transistor parameters are

=−0.7



= 40 μA/V

= 0.015 V

−1

Assume the reference current is

REF

= 160 μA

Solution (DC Analysis): Since M

, M

, and M

are matched transistors, then

= I

REF

= 160 μA

Transistors M

and M

are matched so that in the quiescent condition,

SG3

SD3

SD4

. Since

SG5

SD4

and since the current in

is twice as large as that

, the width-to-length ratio of

must be twice as large as that of M

and M

If we provide dc biases of

GS6

= V

SG7

= 0.85

V to the output transistors, then

the dc quiescent current in the output transistors will be

= I







(

GS6

− V

)





(25)(0.85 − 0.7)

= I

= 22.5 μA

974 Part 2 Analog Electronics

REF

= 5 V

–

= –5 V

Figure 13.15 A three-stage CMOS operational ampliﬁer

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The potential difference across M

must then be

DS8

= 2(0.85) = 1.7

V. We

then have

= I

= 160 =







(

1.7 − 0.7

)

which yields a required width-to-length ratio of

(W/L)

= 4

Solution (AC Analysis): Since there is no loading effect between stages of the

CMOS op-amp, we can write the overall differential voltage gain as

= A

where the gains A

, A

, and A

are the voltage gains of each individual stage. Since

the output stage is a source-follower circuit, we can write that

∼

Deﬁning the differential input voltage as

= v

−v

, the differential voltage

gain of the input stage (using results from Chapter 11) is

= g

r

)

We ﬁnd

= 2















= 2





0.08



(15)



0.16



= 0.438 mA/V

Also

/2)

(0.01)(0.08)

= 1250 k

and

/2)

(0.015)(0.08)

= 833.3k

We then ﬁnd

= (0.438)(1250833.3) = 219

The resistance of M

is relatively small, so the voltage gain of the second common-

source stage is given by

=−g

r

)

We ﬁnd

= 2











= 2





0.04



(80)(0.16)

= 1.012 mA/V

Also

(0.015)(0.16)

= 416.7k

Chapter 13 Operational Ampliﬁer Circuits 975

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and

(0.01)(0.16)

= 625 k

The voltage gain of the second stage is then

=−(1.012)(416.7625) =−253

The overall differential voltage gain of this three-stage CMOS op-amp is then

= A

= (219)(−253) =−55,407

Comment: A reasonable differential voltage gain is obtained in this three-stage

CMOS ampliﬁer.

EXERCISE PROBLEM

Ex 13.10: (a) Calculate the differential voltage gains of the ﬁrst and second stages,

and the overall voltage gain of the three-stage CMOS op-amp in Figure 13.15 if

(W/L)

1,2

= 22.5

and

REF

= 200 μ

A. All other parameters are the same as given

in Example 13.10. (b) Recalculate

(W/L)

if the quiescent current in the output

transistors is to be 40

A. (Ans. (a)

= 240

=−226.2

A =−54, 288

;

(b)

(W/L)

= 4.13)

Folded Cascode CMOS Operational

Ampliﬁer Circuit

As we have mentioned previously, the voltage gain of an ampliﬁer can be increased

by using a cascode conﬁguration. In its simplest form, the conventional cascode

conﬁguration consists of two transistors in series, as shown in Figure 13.16(a). The

13.3.3

976 Part 2 Analog Electronics

~ ~

–

sig

(a) (b)

Figure 13.16 (a) Classical cascode stage. (b) folded-cascode stage

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transistor M

is the common-source amplifying device whose current is determined

by the input voltage. This current is the input signal to M

, which is connected in a

common-gate conﬁguration. The output is taken off the drain of the cascode tran-

sistor. The circuit in Figure 13.16(b) has a slightly different conﬁguration. The dc

current I

in M

is determined by the input voltage. The dc current in M

is the

difference between the bias current I

and I

The ac current in the conventional cascode circuit of Figure 13.16(a) is through

both transistors and the dc power supply. The ac current in the cascode circuit in Fig-

ure 13.16(b) is through both transistors and ground as indicated in the ﬁgure. The ac

current in M

of this circuit is equal in magnitude but in the opposite direction to M

Thus the current is said to be folded back and the circuit in Figure 13.16(b) is called

a folded cascode circuit.

The folded cascode conﬁguration can be applied to the diff-amp as shown in

Figure 13.17. The transistors M

and M

are the differential pair, as usual, and tran-

sistors M

and M

are the cascode transistors. Transistors M

–M

form a modiﬁed

Wilson current mirror acting as an active load. This conﬁguration was discussed in

Chapter 10.

Assuming that transistors M

, M

, and M

–M

are all matched, then the dc cur-

rents in M

and M

are I

REF

/2 and those in M

and M

are I

REF

. This means that the

dc currents in the cascode transistors M

and M

are I

REF

/2.

Chapter 13 Operational Ampliﬁer Circuits 977

–

REF

i = g

Figure 13.17 CMOS folded cascode ampliﬁer

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