Neamen D. Microelectronics: Circuit Analysis and Design
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Solution (for M
1
): We can write that
I
D1
=
k
n1
2
W
L
(V
GS1
− V
TN
)
2
(1 + λ
n
V
DS1
)
From the connection, we see that
V
GS1
= V
DS1
. Then
100 =
80
2
(20)(V
GS1
−0.5)
2
[
1 + (0.02)V
GS1
]
We find that
V
GS1
= V
DS1
= 0.8506
V
Solution (for M
2
): Determine the variation in V
DS2
as a function of x for the poten-
tiometer setting. For
x = 0.3
and
k
n2
= 76 μA/V
2
, we have
R
1
= 135 = 0.97222 k
and
R
2
= 115 = 0.93750 k
Then
V
GS2
= V
GS1
+ I
D1
R
1
− I
D2
R
2
or
V
GS2
= 0.8506 +(0.1)(0.97222) − (0.1)(0.93750)
so
V
GS2
= 0.85407 V
Now
I
D2
=
k
n2
2
W
L
(V
GS2
− V
TN
)
2
(1 + λ
n
V
DS2
)
or
100 =
76
2
(20)(0.85407 − 0.5)
2
[
1 + (0.02)V
DS2
]
which yields
V
DS2
= 2.478 V
Going through the same analysis, the results for other values of x are shown in the
following table as well as the results for
k
n2
= 78 μA/V
2
.
The results are plotted in Figure 14.32.
k
n2
= 76 μA/V
2
k
n2
= 78 μA/V
2
xV
DS2
(V) xV
DS2
(V)
0.3 2.478 0.4 1.696
0.2 1.547 0.3 1.132
0.16 0.9370 0.26 0.8330
0.14 0.5311 0.22 0.4568
1048 Part 2 Analog Electronics
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Comment: By varying the voltage V
DS2
, the applied voltage to the second stage
changes which in turn will change the dc voltage to the output stage. These results
mean that eventually the output voltage can be adjusted to zero for zero input.
We can note that if
k
n2
> k
n1
, then the value x of the potentiometer setting would
be
x > 0.5
.
14.8 SUMMARY
• In this chapter, nonideal effects in op-amp circuits, such as finite open-loop gain,
offset voltage, and bias currents, were considered.
• A finite open-loop amplifier gain results in the magnitudes of the inverting am-
plifier and noninverting amplifier gain being smaller than the ideal values.
• A finite open-loop amplifier gain plus finite input amplifier resistance and
nonzero output resistance results in nonideal op-amp input and output resistance
values.
• The practical op-amp circuit has a finite bandwidth. With negative feedback, the
gain–bandwidth product is essentially constant, so an op-amp circuit with nega-
tive feedback has a reduced gain magnitude but an increased small-signal
bandwidth.
• Slew rate is defined as the maximum rate at which the op-amp output signal can
change per unit time. In general, the slew rate is limited by the internal fre-
quency compensation capacitor. The slew rate is also a function of the bias cur-
rent in the input diff-amp stage.
• An input offset voltage means that the output voltage is not zero when the input
signal voltages are zero. One source of an offset voltage is a mismatch in the dif-
ferential pair transistor parameters and/or mismatches in active load transistor para-
meters. Typically, an offset voltage of a few millivolts may occur in a bipolar cir-
cuit, whereas an offset voltage of tens of millivolts may occur in a MOSFET circuit.
• Input bias currents to an op-amp may range from a few picoamperes for FET input
transistors to as high as a few microamperes for some bipolar input transistors.
• Techniques for offset voltage compensation and input bias current compensation
were analyzed.
• As an application, an offset voltage compensation network was designed for a
CMOS diff-amp.
Chapter 14 Nonideal Effects in Operational Amplifier Circuits 1049
0.1 0.2 0.3 0.4
x
0.5
1.0
1.5
2.0
k
n
′
2
= 76 mA/V
2
k
n
′
2
= 78 mA/V
2
2.5
3.0
V
DS2
(V)
Figure 14.32 Change in drain-to-source voltage as the compensation network is varied
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CHECKPOINT
After studying this chapter the reader should have the ability to:
✓ Understand differences between ideal and practical values of various parameters
of the operational amplifier circuit.
✓ Understand the effect of a finite open-loop amplifier gain on the characteristics
of the op-amp.
✓ Understand the small-signal frequency response and the large-signal slew-rate
response of op-amps.
✓ Understand sources of offset voltage and design various offset voltage compen-
sation circuits for op-amps.
✓ Understand input bias current effects and design input bias current compensa-
tion circuits for an op-amp.
REVIEW QUESTIONS
1. List and describe five practical op-amp parameters and discuss the effect they
have on op-amp circuit characteristics.
2. What is a typical value of open-loop, low-frequency gain of an op-amp circuit?
How does this compare to the ideal value?
3. How does a finite open-loop gain affect the closed-loop gains of the inverting
and noninverting amplifiers?
4. How does a finite open-loop gain affect the (a) input resistance of an op-amp cir-
cuit and (b) the output resistance of an op-amp circuit? Consider the inverting
and noninverting amplifiers.
5. Describe the open-loop amplifier frequency response and define the unity-gain
bandwidth.
6. What is a typical corner frequency value, or dominant-pole frequency, in the
open-loop frequency response?
7. Describe the gain–bandwidth product property of a closed-loop amplifier response.
8. Define slew rate and define full-power bandwidth.
9. What is the primary source of slew-rate limitation in an op-amp circuit?
10. What is one cause of an offset voltage in the input stage of a BJT op-amp?
11. What is one cause of an offset voltage in the input stage of a CMOS op-amp?
12. Describe an offset voltage compensation technique.
13. What is the source of input bias current in the 741 op-amp?
14. What can be the effect of an input bias current?
15. Describe the effect of input bias currents on an integrator.
16. Describe an input bias current compensation technique.
17. Define and explain common-mode rejection ratio.
PROBLEMS
Section 14.1 Practical Op-Amp Parameters
14.1 An op-amp is connected in an inverting amplifier configuration with a volt-
age gain of −80 and is biased at
±5
V. If the output saturates at
±4.5
V,
what is the maximum rms value of an input sine wave that can be applied
without causing distortion in the output signal?
1050 Part 2 Analog Electronics
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14.2 Consider the op-amp described in Problem 14.1. In addition, the maximum
output current of the op-amp is
±15
mA. The resistors used in the configu-
ration are
R
2
= 160
k
and
R
1
= 2
k
. A load resistor R
L
is also connected
from the output terminal to ground. (a) If
R
L
= 1
k
and the output voltage
is
v
O
= 4.5
V, what is the output current of the op-amp and what is the value
of the input voltage? (b) Determine the minimum value of R
L
that can be
used for
v
O
=−4.5V
.
Section 14.2 Finite Open-Loop Gain
14.3 Data in the following table were taken for several op-amps operating in the
open-loop configuration. Determine the unknown variables in the table.
14.4 (a) An inverting amplifier with resistors
R
1
= 5.6
k
and
R
2
= 120
k
is
fabricated using an op-amp with an open-loop gain of
10
5
. What is the per-
cent difference between the actual gain and the ideal gain? (b) Repeat part
(a) if
R
1
is changed to
R
1
= 8.2
k
.
14.5 (a) Consider a noniverting amplifier with
R
1
= 6.8
k
,
R
2
= 47
k
, and an
op-amp with
A
OL
= 2 ×10
4
. (i) What is the closed-loop gain? (ii) Deter-
mine the percent difference between the actual gain and the ideal gain.
(b) Repeat part (a) if
A
OL
= 10
3
.
14.6 (a) An op-amp is ideal except it has a finite open-loop gain of
A
OL
= 2 ×10
3
.
The op-amp is connected in an inverting configuration. Determine
R
2
/R
1
such that the closed-loop voltage gain is
A
CL
=−15.0
. (b) Using the re-
sults of part (a), what is the closed-loop gain if the open-loop gain is
A
OL
= 5 ×10
4
?
14.7 A noninverting amplifier is to be fabricated with a specification of an ideal
closed-loop gain of 90. What is the minimum open-loop gain of the op-
amp such that the closed-loop gain is within 0.01 percent of the ideal
value?
14.8 The output of a voltage follower is to be within 0.02 percent of the ideal
value. What is the minimum op-amp open-loop gain that is required?
14.9 An inverting amplifier is fabricated using 0.1 percent precision resistors.
The nominal resistor values are
R
2
= 210
k
and
R
1
= 21.0
k
. (a) If the
op-amp is ideal, what is the range in the magnitude of voltage gain as a re-
sult of the variation in resistor value? (b) Repeat part (a) if the open-loop
gain of the op-amp is
A
OL
= 10
4
.
14.10 For the op-amp used in the inverting amplifier configuration in Figure
P14.10, the open-loop parameters are
A
OL
= 10
3
and
R
o
= 0
. Determine
the closed- loop gain
A
CL
= v
O
/v
I
and input resistance
R
if
for an open-
loop input differential-mode resistance of: (a)
R
i
= 1
k
,(b)
R
i
= 10
k
,
and (c)
R
i
= 100
k
.
Case A
OL
v
1
v
2
v
O
110
4
−0.1 mV +0.1 mV
22 ×10
3
+10.0 mV 5 V
3 5.50 mV 5.00 mV −10 V
45 ×10
5
0 −4 V
5
−2.010
V
−2.0050
V5 V
Chapter 14 Nonideal Effects in Operational Amplifier Circuits 1051
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14.11 A pressure transducer, as described in Example 14.1, is to be used in conjunc-
tion with a noninverting op-amp circuit. The ideal output voltage is to be +0.10
V for a transducer voltage of 2 mV. Determine the minimum open-loop gain
required so that the actual output voltage is within 0.1 percent of the ideal.
14.12 Consider the two inverting amplifiers in cascade in Figure P14.12. The op-
amp parameters are
A
OL
= 5 ×10
3
,
R
i
= 10
k
, and
R
o
= 1
k
. Deter-
mine the actual closed-loop gains
A
v f 1
= v
o1
/v
i
and
A
v f
= v
o2
/v
i
. What is
the percent error from the ideal values?
14.13 The noninverting amplifier in Figure P14.13 has an op-amp with open-loop
properties:
A
OL
= 10
3
,
R
i
= 20
k
, and
R
o
= 0.5
k
. (a) Determine the
closed-loop values of
A
CL
= v
O
/v
I
,
R
if
, and
R
of
. (b) If
A
OL
decreases by
10 percent, determine the percentage change in
A
CL
.
1052 Part 2 Analog Electronics
100 kΩ
20 kΩ
v
O
v
I
–
+
R
if
Figure P14.10
10 kΩ
100 kΩ
100 kΩ
10 kΩ
v
o2
v
o1
v
i
+
–
+
–
Figure P14.12
v
O
v
I
–
+
R
if
R
of
R
L
= 1 kΩ
40 kΩ
10 kΩ
10 kΩ
+
–
Figure P14.13
v
O
v
I
R
of
+
–
+
–
Figure P14.14
v
O
v
I1
v
I2
20 kΩ
10 kΩ
+
–
40 kΩ
Figure P14.15
14.14 For the op-amp in the voltage follower circuit in Figure P14.14, the open-
loop parameters are
A
OL
= 5 ×10
3
,
R
i
= 10
k
, and
R
o
= 1
k
. (a) Sketch
the small-signal equivalent circuit. (b) Determine the (i) closed-loop voltage
gain
v
O
/v
I
and (ii) output resistance
R
of
.
14.15 The summing amplifier in Figure P14.15 has an op-amp with open-loop
parameters:
A
OL
= 2 ×10
3
,
R
i
=∞
, and
R
o
= 0
. Determine the actual
output voltage as a function of
v
I1
and
v
I2
. What is the percent error from
the ideal value?
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14.16 For the op-amp in the differential amplifier in Figure P14.16, the open-loop
parameters are:
A
OL
= 10
3
,
R
i
=∞
, and
R
o
= 0
. Determine the actual
differential voltage gain
A
d
= v
O
/(v
I2
−v
I1
). What is the percentage error
from the ideal value?
14.17 Because of a manufacturing error, the open-loop gain of each op-amp in
the circuit in Figure P14.17 is only
A
OL
= 100.
The open-loop input and out-
put resistances are
R
i
= 10
k
and
R
o
= 1
k
, respectively. Determine the
closed-loop parameters: (a)
R
if
,(b)
R
of
, and (c)
A
CL
= v
O2
/v
I
. (d) What
is the ratio of the actual closed-loop gain to the ideal value?
Chapter 14 Nonideal Effects in Operational Amplifier Circuits 1053
v
O
v
I1
10 kΩ
10 kΩ
40 kΩ
40 kΩ
v
I2
–
+
Figure P14.16
1 kΩ
1 kΩ
v
O1
v
I
100 Ω
100 Ω
v
O2
R
if
R
of
+
–
+
–
+
–
Figure P14.17
Section 14.3 Frequency Response
14.18 An inverting amplifier has a closed-loop voltage gain of
−25
. The op-amp
used has a low-frequency, open-loop gain of
2 × 10
4
and has a unity-gain
bandwidth of 10
6
Hz. (a) What is the 3 dB frequency
f
3-dB
of the op-amp
and the 3 dB frequency
f
3-dB
of the closed-loop amplifier? (b) Using the re-
sults of part (a), what is the magnitude of the voltage gain for the open-loop
and closed-loop amplifiers at
f = 0.25 f
3-dB
and at
f = 5 f
3-dB
?
14.19 The open-loop low-frequency gain of an op-amp is
A
o
= 100
dB. At a fre-
quency of
f = 10
4
Hz, the magnitude of the open-loop gain is 38 dB.
Determine the dominant-pole frequency and the unity gain bandwidth.
14.20 A noninverting amplifier uses 5 percent precision resistors with nominal
values of
R
2
= 150
k
and
R
1
= 15
k
. The op-amp has a low-frequency
gain of
A
o
= 3 ×10
4
and has a unity-gain bandwidth of
f
T
= 1.2
MHz.
(a) What is the nominal low-frequency closed-loop gain and bandwidth?
(b) Determine the range in low-frequency closed-loop gain and bandwidth.
14.21 The low-frequency open-loop gain of an op-amp is
2 × 10
5
and the second
pole occurs at a frequency of 5 MHz. An amplifier using this op-amp has a
low-frequency closed-loop gain of 100 and a phase margin of 80 degrees.
Determine the dominant-pole frequency.
14.22 Two inverting amplifiers are connected in cascade to provide an overall
voltage gain of 500. The gain of the first amplifier is
−10
and the gain of the
second amplifier is
−50
. The unity-gain bandwidth of each op-amp is
1 MHz. (a) What is the bandwidth of the overall amplifier system? (b) Re-
design the system to achieve the maximum bandwidth. What is the maxi-
mum bandwidth?
14.23 Three inverting amplifiers, each with
R
2
= 150
k
and
R
1
= 15
k
,are
connected in cascade. Each op-amp has a low-frequency gain of
A
o
= 5 ×10
4
and a unity-gain bandwidth of
f
T
= 1.5
MHz. (a) Determine
the low-frequency closed-loop gain and the
−3
dB frequency of each stage.
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(b) Determine the low-frequency closed-loop gain and the
−3
dB frequency
of the overall system.
14.24 An inverting amplifier circuit has a voltage gain of
−25
. The op-amp used
in the circuit has a low-frequency voltage gain of
5 × 10
4
and a unity-gain
bandwidth of 1 MHz. Determine the dominant pole frequency of the op-
amp and the small-signal bandwidth,
f
3-dB
, of the inverting amplifier. What
is the magnitude of the closed-loop voltage gain at
0.5 f
3-dB
and at
2 f
3-dB
?
14.25 An audio amplifier system, using a noninverting op-amp circuit, needs to
have a small-signal bandwidth of 20 kHz. The open-loop low-frequency
voltage gain of the op-amp is 10
5
and the unity-gain bandwidth is 1 MHz.
What is the maximum closed-loop voltage gain that can be obtained for
these specifications?
14.26 If an op-amp has a slew-rate of 5
V/μ
s, find the full-power bandwidth for a
peak output voltage of (a) 5 V, (b) 1.5 V, and (c) 0.4 V.
14.27 (a) An op-amp with a slew rate of 8 V/
μ
s is driven by a 250 kHz sine wave.
What is the maximum output amplitude at which slew-rate limiting is
reached? (b) Repeat part (a) for a 250 kHz zero time-average triangular wave.
D14.28 An amplifier system is to be designed to provide an undistorted 10 V peak
sinusoidal signal at a frequency of
f = 12
kHz. Determine the minimum
slew rate required for the amplifier.
14.29 (a) The op-amp to be used in the audio amplifier system in Problem 14.25
has a slew rate of 0.63
V/μs
. Determine the peak value of undistorted output
voltage that can be achieved. (b) Repeat part (a) if the slew rate is 3
V/μs
.
14.30 The op-amp in the noninverting amplifier configuration in Figure Pl4.30 has
a slew rate of 1 V/
μ
s. Sketch the output voltage versus time for each of the
three inputs shown. The op-amp is biased at
±10
V.
1054 Part 2 Analog Electronics
10 kΩ
40 kΩ
v
O
v
I
+
–
+
–
v
I
(volts)
Time (ms)1
109
0.1
0.4
1.0
0
(a)
(b)
(c)
Figure P14.30
10 kΩ
30 kΩ
10 kΩ
20 kΩ
v
O2
v
O1
v
I
v
I
(volts)
Time (ms)
1
2019
0.5
1.0
0
(a)
(b)
–
+
–
+
Figure P14.31
14.31 For each op-amp in the circuit shown in Figure P14.31, the bias is
±15
V
and the slew rate is 3 V/
μ
s. Sketch the output voltages
v
O1
and
v
O2
versus
time for each input shown.
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Section 14.4 Offset Voltage
14.32 For the transistors in the diff-amp in Figure 14.16 in the text, the current
parameters I
S1
and I
S2
can be written as
5 × 10
−14
(1 + x) A
, where x repre-
sents the deviation from the ideal due to variations in electrical and geomet-
ric characteristics. (The value of x is positive for one transistor and negative
for the other transistor.) Determine the maximum value of x such that the
maximum offset voltage is limited to
V
OS
= 2.5
mV.
14.33 The bipolar active load diff-amp in Figure 14.18 is biased at
V
+
= 5
V and
V
−
=−5
V. The transistor parameters are
V
AN
= 120
V,
V
AP
= 80
V,
v
BE
(
npn
)
= v
EB
(
pnp
)
= 0.6
V,
I
S1
= I
S2
, and
I
S3
= 5 ×10
−15
A. Let
v
1
= v
2
. Determine the value of
I
S4
for which
Q
4
has a C–E voltage of
(a)
v
EC4
= 0.6
V, (b)
v
EC4
= 1.2
V, and (c)
v
EC4
= 2.5
V.
14.34 For the transistors in the diff-amp in Figure 14.19, the conduction parame-
ters can be written as
150
(
1 + x
)
μA/V
2
, where
x
represents the deviation
from the ideal due to variations in electrical and geometric characteristics.
(The value of
x
is positive for one transistor and negative for the other tran-
sistor.) Assume
I
Q
= 200 μ
A and
V
TN1
= V
TN2
= 0.4
V. Determine the
maximum value of
x
such that the maximum offset voltage is limited to
V
OS
= 15
mV.
14.35 (a) An inverting op-amp circuit has a gain of
−30
. The op-amp used in the
circuit has an offset voltage of
±2
mV. If the input signal voltage to the am-
plifier is 10 mV, determine the possible range in the output voltage. (b) Re-
peat part (a) if the input signal voltage is 100 mV.
14.36 Repeat Problem 14.35 for an input signal voltage of
v
I
= 25 sin ω t
(mV).
14.37 Consider the integrator circuit in Figure P14.37. The circuit parameters are
R = 10 k
and
C = 10 μ
F. The op-amp offset voltage is
±5
mV. For
v
i
= 0
, determine the output voltage versus time. For the worst-case offset
voltage, determine the time that it would take for the output voltage to reach
±5
V.
Chapter 14 Nonideal Effects in Operational Amplifier Circuits 1055
v
o
v
i
C
R
–
+
Figure P14.37
10 kΩ
100 kΩ
v
O1
v
I
10 kΩ
50 kΩ
v
O2
+
–
–
+
–
+
Figure P14.38
14.38 In the circuit in Figure P14.38, the offset voltage of each op-amp is
±3
mV.
(a) Determine the possible range in output voltages
v
O1
and
v
O2
for
v
I
= 0
.
(b) Repeat part (a) for
v
I
= 10
mV. (c) Repeat part (a) for
v
I
= 100
mV.
(d) Design offset voltage compensation circuit(s) to adjust both
v
O1
and
v
O2
to zero when
v
I
= 0
.
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14.39 In the circuit shown in Figure P14.39, the op-amp is ideal. For
v
I
= 0.5
V,
determine
v
O
when the wiper arm of the potentiometer is at the
V
+
node, in
the center, and at the
V
−
node.
1056 Part 2 Analog Electronics
14.40 Consider the bipolar diff-amp with an active load and a pair of offset-null
terminals as shown in Figure 14.22 in the text. Let
R
1
= R
2
= 500
and
let R
x
be a 50 k
potentiometer. (a) If the wiper arm of the potentiometer is
exactly in the center, determine the effective resistances
R
1
and
R
2
. (b) As-
sume
I
Q
= 250 μ
A meaning that
i
C1
= i
C2
= 125 μ
A. Let
I
S3
=
2 × 10
−14
A
and
I
S4
= 2.2 ×10
−14
A
. Determine the required values of x
and (
1 − x
) of the potentiometer to compensate for the transistor mismatches.
14.41 The bipolar diff-amp in Figure 14.22 in the text is biased at
I
Q
= 500 μ
A.
Assume all transistors are matched, with
I
S
= 10
−14
A
. Let
R
1
= R
2
=
500
, and assume R
x
is a 50 k
potentiometer. If the wiper arm of the po-
tentiometer is off center such that
x = 15
k and
(1 − x) = 35 k
, deter-
mine the ratio of
i
C1
/i
C2
. What is the corresponding offset voltage?
Section 14.5 Input Bias Current
14.42 (a) An op-amp is connected in an inverting amplifier configuration with
R
2
= 200
k
and
R
1
= 20
k
. The input bias current at the inverting ter-
minal is
1 μ
A and the input bias current at the noninverting terminal is
2 μ
A. Design a bias current compensated amplifier. (b) Repeat part (a) if the
input bias current at the inverting terminal is
0.8 μ
A and the input bias cur-
rent to the noninverting terminal is
0.5 μ
A.
14.43 An inverting amplifier has parameters
R
2
= 150
k
and
R
1
= 15
k
. Bias
currents of
2 μ
A are leaving each op-amp terminal. Determine the output
voltage if the input voltage is (a)
v
I
= 0
,(b)
v
I
= 20
mV, (c)
v
I
=−20
mV,
and (d)
v
I
= 100
mV.
14.44 An op-amp is connected in a noninverting amplifier configuration with a
voltage gain of
+41
. The feedback resistor is 250 k
. The op-amp has input
bias currents of
I
B1
= I
B2
= 0.6 μ
A. Determine the output voltage
v
O
for
input voltages of (a)
v
I
= 0
,(b)
v
I
= 8
mV, (c)
v
I
=−3.5
mV, and
(c)
v
I
= 5 sin ωt
(mV).
D14.45 An op-amp used in a voltage follower configuration is ideal except that
the input bias currents are
I
B1
= I
B2
= 1 μ
A. The source driving the volt-
age follower has an output resistance of 10 k
. (a) Find the output voltage
due to the bias current effects when
v
I
= 0
. (b) Can the circuit be designed
to compensate for the input bias currents? If so, how?
v
O
v
I
R
4
= 10 kΩ
14.46 In the differential amplifier in Figure P14.16, the op-amp is ideal except that
the average input bias current is
I
B
= 10 μ
A and the input offset current is
I
OS
= 3 μ
A. If
v
i1
= v
i2
= 0
, determine the worst-case output voltage
v
O
due to the input bias current effects.
D14.47 The op-amp bias currents for the circuit in Figure P14.38 are equal at
I
B1
=
I
B2
= 1 μ
A. (a) Find the worst-case output voltages
v
O1
and
v
O2
for
v
I
= 0
.
(b) Design input bias current compensation circuit(s) to adjust both
v
O1
and
v
O2
to zero when
v
I
= 0
.
14.48 (a) For the integrator circuit in Figure P14.48, let the input bias currents be
I
B1
= I
B2
= 0.1 μ
A. Assume that switch S opens at
t = 0
. Derive an ex-
pression for the output voltage versus time for
v
I
= 0
. (b) Plot
v
O
versus
time for
0 ≤ t ≤ 10
s. (c) Repeat part (b) for
I
B1
= I
B2
= 100
pA.
Chapter 14 Nonideal Effects in Operational Amplifier Circuits 1057
R = 50 kΩ
S
v
I
v
O
I
B1
I
B2
C = 1 m F
+
–
–
+
Figure P14.48
10 kΩ
50 kΩ
v
O1
R
A
v
I
R
B
20 kΩ
20 kΩ
v
O3
v
O2
+
–
–
+
–
+
–
+
Figure P14.49
50 kΩ
25 kΩ
50 kΩ
v
O
50 kΩ
1 MΩ
50 kΩ
v
O
(a) (b)
–
+
–
+
Figure P14.50
14.49 For the circuit in Figure P14.49, the op-amps are ideal except that the op-
amps have bias currents of
I
B
= 3 μ
A entering each op-amp terminal.
(a) For
v
I
= 0
and
R
A
= R
B
= 0
, determine the values of
v
O1
,
v
O2
, and
v
O3
. (b) Determine the values of
R
A
and
R
B
for input bias current compen-
sation. (c) If the average input bias current is
I
B
= 3 μ
A and the input off-
set current is
I
OS
= 0.3 μ
A, determine the worst-case output values of
v
O1
,
v
O2
, and
v
O3
using the results of part (b).
14.50 For each circuit in Figure P14.50, the input bias current is
I
B
= 0.8 μ
A the
input offset current is
I
OS
= 0.2 μ
A. (a) Determine the output voltage due
to the average bias current I
B
. (b) Determine the worst-case output voltage,
including the effect of the input offset current.
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