Neamen D. Microelectronics: Circuit Analysis and Design

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1028 Part 2 Analog Electronics

EXERCISE PROBLEM

Ex 14.6: A 0.5 V input step function is applied at

t = 0

to a noninverting ampli-

ﬁer with a closed-loop gain of 8. The slew rate of the op-amp is 1.25 V/

Determine the output voltage at (a) (i)

t = 2 μ

s, (ii)

t = 4 μ

s, and (iii)

t = 6 μ

(b) At what time does the output reach its full scale response? (Ans. (a) (i) 2.5 V,

(ii)

V, (iii) 4 V; (b)

3.2 μ

Typical slew-rate values for the CA3140 BiCMOS and LH0042C BiFET

op-amps are also given in Table 14.1. The BiCMOS circuit has a typical slew rate of

9V/

s, and the BiFET op-amp has a typical value of 3 V/

s. The slew rates are

larger in the FET op-amps because the bias currents are larger than in the 741 circuit

and the gain of the FET input stage is smaller than that of the 741 input stage.

The slew rate is directly related to the unity-gain bandwidth. To explain, the

unity-gain bandwidth is directly proportional to the dominant-pole frequency, or

∝ f

. In turn, the dominant-pole frequency is inversely proportional to

where

is the equivalent resistance at the node of the second stage input and

the compensation capacitance. The equivalent resistance

is a function of the sec-

ond stage input resistance and the diff-amp stage output resistance, both of which are

inversely proportional to

. Then,

∝ f

∝





∝

(14.51)

where

is the slew rate. Equation (14.51) shows that the slew rate is directly

proportional to the unity-gain bandwidth.

Now consider what happens when a sinosoidal input signal is applied, for ex-

ample, to the noninverting ampliﬁer shown in Figure 14.9. If

= V

sin ωt

, then

(t) = V



1 +



sin ωt = V

sin ωt

(14.52)

where

is the ideal peak value of the sinusoidal output voltage.

The rate at which the output voltage changes is

(t)

= ωV

cos ωt

(14.53)

Therefore, the maximum rate of change is

ωV

. Figure 14.13 shows two sinusoidal

waveforms of the same frequency but different peak amplitudes. The maximum rate of

(t)

Time

Slope = –SR Slope = +SR

Figure 14.13 Two sinusoidal waveforms of the same frequency with different peak voltages,

showing different maximum slopes

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change, or slope, occurs as the curves cross the zero axis. The waveform with the larger

peak value has a larger maximum slope. Curve

in Figure 14.13 has a maximum slope

corresponding to the slew rate; curve

, with a smaller peak value, has a maximum

slope less than the slew rate. If the maximum slope,

ωV

, is greater than the slew rate

SR, then the op-amp is slew-rate-limited and the output signal is distorted.

Thus, the maximum frequency at which the op-amp can operate without being

slew-rate-limited is a function of both the frequency and peak amplitude of the signal.

We have that

max

= 2π f

max

= SR

(14.54(a))

max

2π V

(14.54(b))

As the output voltage peak amplitude increases, the maximum frequency at which

slew-rate-limiting occurs decreases. The full-power bandwidth (FPBW) is the fre-

quency at which the op-amp output becomes slew-rate-limited. The FPBW is the

max

frequency from Equation (l4.54(b)), or

FPBW =

2π V

(14.55)

The full-power bandwidth can be considerably less than the small-signal bandwidth.

EXAMPLE 14.7

Objective: Determine the small-signal bandwidth of an ampliﬁer and the full-power

bandwidth that will produce an undistorted output voltage.

Consider an ampliﬁer with a unity-gain bandwidth of

= 1

MHz and a low-

frequency closed-loop gain of

CLO

= 10

. Assume the op-amp slew rate is

SR = 1V/μs

and the desired peak output voltage is

= 10

Solution: The small-signal closed-loop bandwidth is, from Equation (14.44),

3-dB

CLO

⇒ 100 kHz

The full-power bandwidth, based on slew-rate limitation, from Equations (14.54(b))

and (14.55), is

max

= FPBW =

2π V

(1V/μs)(10

μs/s)

2π(10)

⇒ 15.9 kHz

Comment: The full-power bandwidth, or the actual maximum frequency at which

the system can be operated and still produce a large, undistorted output signal, is

considerably smaller than the bandwidth under small-signal nonslew-rate-limiting

conditions.

EXERCISE PROBLEM

Ex 14.7: The slew rate of the 741 op-amp is 0.63 V/

s. Determine the full-power

bandwidth for a peak undistorted output voltage of (a) 0.25 V, (b) 2 V, and (c) 8 V.

(Ans. (a) 401 kHz, (b) 50.1 kHz, (c) 12.5 kHz)

Chapter 14 Nonideal Effects in Operational Ampliﬁer Circuits 1029

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Test Your Understanding

TYU 14.8 (a) An op-amp is connected in an inverting configuration. The para-

meters of the op-amp are

= 5 ×10

= 15

Hz, and

SR = 0.8

s. The

low-frequency closed-loop gain is

CLO

= 25

. (i) What is

3-dB

of the closed-loop

system? (ii) If

max

= f

3-dB

, determine the maximum undistorted output voltage am-

plitude. (b) Repeat part (a) if the op-amp parameters are

= 5 ×10

= 10

Hz, and

SR = 0.8

s. (Ans. (a) (i)

3-dB

= 30

kHz, (ii)

= 4.24

(b) (i)

3-dB

= 200

kHz, (ii)

= 0.637

14.4 OFFSET VOLTAGE

Objective: • Deﬁne and analyze sources and effects of offset voltage.

In Chapter 11, we analyzed the basic difference ampliﬁer, which is the input stage of the

op-amp. In that analysis, we assumed the input differential-pair transistors to be identi-

cal, or matched. If the two input devices are mismatched, the currents in the two branches

of the diff-amp are unequal and this affects the diff-amp dc output voltage. In fact, the

internal circuitry of the entire op-amp usually contains imbalances and asymmetries, all

of which can cause a nonzero output voltage for a zero input differential voltage.

The output dc offset voltage is the measured open-loop output voltage when

the input voltage is zero. This conﬁguration is shown in Figure 14.14. The input dc

offset voltage is deﬁned as the input differential voltage that must be applied to the

open-loop op-amp to produce a zero output voltage. This conﬁguration is shown in

Figure 14.15. The input offset voltage is the parameter most often speciﬁed and is

usually referred to simply as the offset voltage.

Offset voltage values have a statistical distribution among op-amps of the same

type, and the offset voltage polarity may vary from one op-amp to another. The offset

voltage speciﬁcation for an op-amp is the magnitude of the maximum offset voltage

for a particular type of op-amp. The offset voltage is a dc value, generally in the range

of 1 to 2 mV for bipolar op-amps, although some op-amps may have offset voltages

in the range of 5 to 10 mV. Further, the maximum offset voltage speciﬁcation for a

precision op-amp may be as low as 10

In this section we will analyze offset voltage effects in the input diff-amp stage

and will then consider various techniques used to compensate for offset voltage.

Input Stage Offset Voltage Effects

Several possible mismatches in the input diff-amp stage can produce offset voltages.

We will analyze offset voltage effects in two bipolar input stages and in a MOSFET

input diff-amp circuit.

Basic Bipolar Diff-Amp Stage

A basic bipolar diff-amp is shown in Figure 14.16. The differential pair is biased with

a constant-current source. If

and

are matched, then for

= v

= 0, I

splits

evenly between the two transistors and

= i

. If a two-sided output is deﬁned as

14.4.1

1030 Part 2 Analog Electronics

–

= 0

–

Figure 14.15 Circuit for

measuring input offset

voltage

–

Figure 14.14 Circuit for

measuring output offset

voltage

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the difference in voltage between the two collector terminals, then

= 0

when the

transistors are matched and the collector resistors are matched, which means that

the offset voltage is zero.

The collector currents can be written as

= I

BE1

(14.56(a))

and

= I

BE2

(14.56(b))

where

and

are related to the reverse-saturation currents in the B–E junctions

and are functions of the electrical and geometric transistor properties. If the two tran-

sistors are exactly matched, then

= I

; if there is any mismatch in the electrical

or geometric parameters, then

= I

The input offset voltage is deﬁned as the input differential voltage required to

produce a zero output voltage, or in this case to produce

= i

. Figure 14.17

shows the

versus

characteristics of two unmatched transistors. Slightly dif-

ferent B–E voltages must be applied to produce equal collector currents that will

result in a zero output voltage in the diff-amp.

For

= i

, we have

BE1

= I

BE2

(14.57)

BE1

−v

BE2

)/V

(14.58)

We deﬁne the offset voltage as

BE1

−v

BE2

≡ V

Since

−v

= v

BE1

−v

BE2

, then the offset voltage

is the differential

input voltage that must be applied to produce

= i

Equation (14.58) can then be written as

(14.59(a))

Chapter 14 Nonideal Effects in Operational Ampliﬁer Circuits 1031

–

BE1

BE2

Figure 14.16 Basic bipolar

difference ampliﬁer

Figure 14.17 The

versus

characteristics for two unmatched

bipolar transistors

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= V





(14.59(b))

EXAMPLE 14.8

Objective: Calculate the offset voltage in a bipolar diff-amp for a given mismatch

between the input transistors.

Consider the diff-amp in Figure 14.16 with transistor parameters

=10

−14

and

=1.05 ×10

−14

Solution: From Equation (14.59(b)), the offset voltage is

= V





= (0.026) ln



1.05 × 10

−14

1 × 10

−14



= 0.00127 V ⇒ 1.27 mV

Comment: A 5 percent difference in

for

and for

produces an offset volt-

age of 1.27 mV. Since the offset voltage is deﬁned as a positive quantity, if in the pre-

vious example

were 5 percent larger than

, the offset voltage would also be

1.27 mV.

EXERCISE PROBLEM

Ex 14.8: Consider the bipolar diff-amp in Figure 14.16. For

, assume

= 2 ×10

−15

A. If the offset voltage is

= 2

mV, what is the percent dif-

ference in the value of

compared to

? (Ans. 8 percent)

It should be cautioned that the offset voltage in this example is one component

of the offset voltage for the entire op-amp. For example, if the two collector resistors

are not equal, then the two-sided output voltage

will not be zero even if the two

transistors are identical. Nevertheless, the calculation provides information on one

source of offset voltage, as well as the resulting magnitude of

Bipolar Active Load Diff-Amp Stage

Figure 14.18 shows a bipolar diff-amp with a simple two-transistor active load. As

before, this input stage is biased with a constant-current source. If

and

are

matched and if

and

are matched, then

splits evenly between

and

for

= v

, and the E–C voltages of

and

are equal. The one-sided dc output volt-

age

will therefore be one E–B voltage below

If, however,

and

are not exactly matched, then

and

may not be

equal since the active load inﬂuences the split in the bias current, even if

and

are matched. This effect is caused by a ﬁnite Early voltage. Taking the Early

voltages into account, but neglecting base currents, we can write the collector

currents as

= i

= I

BE1

)



1 +

CE1



= I

EB3

)



1 +

EC3



(14.60(a))

1032 Part 2 Analog Electronics

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and

= i

= I

BE2

)



1 +

CE2



= I

EB4

)



1 +

EC4



(14.60(b))

If we assume that

and

are matched, then

= I

≡ I

and

≡ V

. Assume that

and

are slightly mismatched, so that

= I

but

still assume that

= V

≡ V

. For

= v

, we have

BE1

= v

BE2

; also,

EB3

= v

EB4

= v

EC3

≡ v

. Taking the ratio of Equations (14.60(a)) and (14.60(b))

produces

1 +

CE1

1 +

CE2

1 +

EC4

(14.61)

Equation (14.61) can be rearranged in the form

1 +

CE1

1 +

CE2

1 +

EC4

(14.62)

Since

is connected as a diode,

CE1

is a constant for a given bias current and

supply voltage, which means that the left side of Equation (14.62) is a constant. If

= I

, then

CE2

= v

CE1

and

EC4

= v

EC3

.However,if

= I

, then the

collector–emitter voltages on

and

must change. If, for example,

> I

, then

EC4

must increase and

CE2

must decrease in order to keep Equation (14.62) balanced.

If, on the other hand,

> I

, then

CE2

must increase and

EC4

must decrease. A

decrease in

EC4

means that

may be driven into saturation by the mismatch.

Chapter 14 Nonideal Effects in Operational Ampliﬁer Circuits 1033

–

Figure 14.18 Basic bipolar diff-amp with active load

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EXAMPLE 14.9

Objective: Calculate the change in output voltage for a given mismatch in the active

load transistors.

Consider the diff-amp in Figure 14.18 with

= 10

V. Assume that

and

are matched with

BE1

= v

BE2

= 0.6

V, and assume that

EB3

= v

EB4

= v

EC3

0.6 V. Let

= 1.05I

. Also assume that

= V

= 50

Solution: Since

EB3

= 0.6V= v

BE1

, then for

= v

= 0

CE1

= V

= 10 V

The left side of Equation (14.62) is therefore

1 +

CE1

1 +

0.6

= 1.186

We have that

EC4

CE2

= V

BE2

= 10.6V

CE2

= 10.6 −v

EC4

Equation (14.62) then becomes

1.186 = 1.05

1 +

10.6 − v

EC4

1 +

EC4

which yields

EC4

= 1.94 V

Comment: A 5 percent difference between the properties of

and

produces a

change from 0.6 to 1.94 V in the E–C voltage of

Computer Simulation Veriﬁcation: A PSpice analysis of the offset voltage effects in

the active load diff-amp was performed. The two input terminals are at ground

potential.

Using

= 5 ×10

−15

for all transistors, the PSpice analysis shows that

EB3

= 0.654

V rather than the assumed value of 0.6 V. Also,

EC4

is 1.19 V rather

than equal to

EB3

. This occurs because the circuit is slightly unbalanced; that is,

includes the base currents of

and

, and

does not. When

and

are not

matched and

= 1.05I

= 5.25 ×10

−15

, then

EC4

increases to 2.51 V, com-

pared to 1.94 V from the hand analysis. If, however,

= 0.95I

= 4.75 ×10

−15

then

goes into saturation.

EXERCISE PROBLEM

*Ex 14.9: Consider the active load bipolar diff-amp stage in Figure 14.18. Assume

the circuit and transistor parameters are as given in Example 14.9. Using Equa-

tions (14.60(a)) and (14.60(b)), determine the offset voltage

=|v

BE2

−v

BE1

such that

EC3

= v

EC4

and

CE1

= v

CE2

. (Ans. 1.27 mV)

1034 Part 2 Analog Electronics

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An offset voltage that will slightly change

and

will allow the E–C volt-

age of

to be adjusted back to its original value.

As shown in actual op-amp circuits, resistors are usually included in the emitters

of the active load transistors. By producing a slight imbalance in the two resistor val-

ues, we can change the ratio of

, causing a change in the output voltage. This

is discussed in the next section when offset voltage null adjustment is discussed.

MOSFET Diff-Amp Stage

Figure 14.19 shows a basic MOSFET diff-amp in which the differential pair is biased

with a constant-current source. If

and

are matched, then for

= v

= 0, I

splits evenly between the two transistors and

= i

. Since a two-sided output is

the voltage difference between the two drain terminals, then for this symmetrical

situation,

= 0

and the offset voltage is zero.

Chapter 14 Nonideal Effects in Operational Ampliﬁer Circuits 1035

–

––

GS1

GS2

Figure 14.19 Basic MOSFET diff-amp

The drain currents can be written as

= K

GS1

− V

TN1

)

(14.63(a))

and

= K

GS2

− V

TN2

)

(14.63(b))

As previously stated, the conduction parameters

and

are functions of

the electrical and geometric properties of the two transistors, and the threshold volt-

ages

TN1

and

TN2

are also functions of the transistor electrical properties. If there

is a mismatch in electrical or geometric parameters, then we may have

= K

and

TN1

= V

TN2

As with the bipolar diff-amp, the input offset voltage is deﬁned as the input dif-

ferential voltage that must be applied to produce a zero output voltage, or

= v

GS1

−v

GS2

(14.64)

When the offset voltage is applied,

= i

= I

; when the two drain resistors

are equal, then

= 0

. Solving Equations (14.63(a)) and (14.63(b)) for

GS1

and

GS2

and substituting the results into Equation (14.64), we ﬁnd



+ V

TN1

−





+ V

TN2



(14.65)

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The various difference and average quantities are deﬁned as follows:

K

= K

− K

(14.66(a))

+ K

(14.66(b))

V

= V

TN1

− V

TN2

(14.67(a))

and

TN1

+ V

TN2

(14.67(b))

Combining Equations (14.66(a)) and (14.66(b)), we have

= K

K

(14.68(a))

and

= K

−

K

(14.68(b))

Similarly,

TN1

= V

V

(14.69(a))

and

TN2

= V

−

V

(14.69(b))

Noting that

= i

= I

and substituting Equations (14.68(a)) through

(14.69(b)) into Equation (14.65), we obtain





√

+(K

/2)

−

√

−(K

/2)



+V

(14.70)

If we assume that

K

 K

then Equation (14.70) reduces to

=−





K



+V

(14.71)

Equation (14.71) is the offset voltage in a MOSFET diff-amp as a function of the

differences in conduction parameters and threshold voltages.

EXAMPLE 14.10

Objective: Calculate the offset voltage in a MOSFET diff-amp stage for a given

mismatch between input transistors.

Consider the diff-amp in Figure 14.19 with transistor parameters

105 μA/V

= 100 μA/V

, and

TN1

= V

TN2

. Assume

= 200 μ

Solution: From Equation (14.66(a)), the difference in conduction parameters is

K

= K

− K

= 105 −100 = 5 μA/V

1036 Part 2 Analog Electronics

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From Equation (14.66(b)), the average of the conduction parameters is

+ K

105 + 100

= 102.5 μA/V

The magnitude of the offset voltage is, from Equation (14.71),





K





200

2(102.5)



102.5



= 0.0241 V ⇒ 24.1mV

Comment: A 5 percent difference in conduction parameter values between the input

MOS transistors produces an offset voltage of 24.1 mV.

EXERCISE PROBLEM

Ex 14.10: Assume the MOSFET diff-amp shown in Figure 14.19 is biased with a

current

= 150 μA

. Let

TN1

= V

TN2

. Assume the nominal conduction para-

meter value is

= 50 μA/V

. Determine the maximum variation

K

such that

the offset voltage is limited to

= 20

mV. (Ans.

K

= 1.63 μA/V

)

Comparing the results of Examples 14.8 and 14.10 shows that typically the

offset voltage for a MOSFET diff-amp is substantially larger than that of a bipolar

diff-amp. The difference can be explained by comparing Equation (14.71) for the

MOSFET diff-amp and Equation (14.59(b)) for the bipolar diff-amp. The offset volt-

age for the MOSFET diff-amp is directly proportional to the percent change in

conduction parameter values, whereas the offset voltage for the bipolar diff-amp is

proportional to the logarithm of the percent change in the

current parameters. In

addition, the offset voltage for the MOSFET pair is proportional to



= V

− V

which is typically in the range of 0.3–2 V. In contrast, the offset voltage for the bipo-

lar pair is proportional to

∼

26 mV

which is substantially smaller than

− V

)

. Thus, a MOSFET diff-amp inher-

ently displays a higher input offset voltage than a bipolar pair for the same level of

mismatch.

Partial data sheets showing some of the nonideal characteristics for the op-amps

considered in the last chapter are in Table 14.1. The 741 op-amp, an all-bipolar

circuit, has a maximum input offset voltage of 3 mV. The CA3140, which has a

MOSFET input differential pair, has a maximum input offset voltage of 15 mV;

and the LH0042C, which has a JFET input differential pair, has a maximum input

offset voltage of 20 mV. This supports our conclusion that op-amps with FET input

transistors have substantially larger input offset voltages than the all-bipolar cir-

cuit discussed.

Offset Voltage Compensation

In many applications, especially those for which the input signal is large compared to

the offset voltage V

, the effect of the offset voltage is negligible. However, there are

14.4.2

Chapter 14 Nonideal Effects in Operational Ampliﬁer Circuits 1037

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