Neamen D. Microelectronics: Circuit Analysis and Design

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1298 Part 3 Digital Electronics

necessary current drive. One example of a BiCMOS logic circuit is shown in Figure

17.37. This is a two-input NOR gate. As seen in the ﬁgure, the CMOS conﬁguration

is the same as the basic CMOS NOR logic gate considered previously. The two npn

output transistors and the

and

resistors have the same conﬁguration and pur-

pose as was seen in the BiCMOS inverter.

Other BiCMOS logic circuits are designed in a manner similar to that shown for

the BiCMOS NOR gate.

17.6 DESIGN APPLICATION: A STATIC ECL GATE

Objective: • Design a static ECL gate to implement a speciﬁc logic

function.

Speciﬁcations: A static ECL gate is to be designed to implement the logic function

Y = (A + B)(C + D)

. The circuit is to be designed using constant current sources

and the total power dissipation is to be no more than approximately 1 mw.

Design Approach: A modiﬁed static ECL gate with a Schottky diode similar to the

circuit conﬁguration in Figure 17.10 is to be designed.

Choices: Inputs A, B, C, and D are assumed to be available. Simple two-transistor

current sources will be used.

Figure 17.37 Two-input BiCMOS NOR circuit

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Chapter 17 Bipolar Digital Circuits 1299

= 1.7 V

REF

D C

Figure 17.38 The static ECL gate for the design application

Solution (DC Circuit Design): There are four basic currents in the circuit. Assum-

ing that each bias current

is equal to the reference current

REF

, then from the total

power dissipation, we ﬁnd

= 1 = I

= 4I

(1.7)

which yields

∼

0.15 mA

From the reference current leg of the circuit, we have

− V

(on)

REF

1.7 − 0.7

0.15

= 6.7k

When either of the reference transistors

is turned on, we would like the

currents in

and

to be equal. Assuming the Schottky diode turn-on voltage to

= 0.4V

, we then ﬁnd

0.4

0.075

= 5.3k

The reference voltage is to be set at

= 1.5V

(the average of the logic 0 and

logic 1 output voltages). The resistance

is then found from

− V

1.7 − 1.5

0.15

= 1.3k

Comment: The entire circuit will be fabricated as an integrated circuit, so standard-

valued resistors are not required in the design.

Solution (Basic Conﬁguration): The circuit in Figure 17.10 performs the OR logic

function. To implement the AND logic function, we can effectively tie the outputs of

two OR logic gates together. Figure 17.38 shows the logic gate conﬁguration. We can

show that the output Y is indeed the logic function desired.

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1300 Part 3 Digital Electronics

17.7 SUMMARY

• This chapter presented the analysis and design of bipolar digital logic circuits,

which were historically the ﬁrst logic circuit technology used in digital systems.

• Emitter-coupled logic (ECL) is used in specialized high-speed applications. The

basic ECL gate has the same conﬁguration as the differential ampliﬁer, but tran-

sistors are switched between cutoff and the active region. Avoiding driving tran-

sistors into saturation keeps the propagation delay time to a minimum.

• The classical ECL gate uses the diff-amp conﬁguration in conjunction with

emitter-follower output stages and a reference voltage circuit. Both NOR and

OR outputs are available.

• Modiﬁed ECL logic gates can be designed with reduced power dissipation.

• The analysis of diode-transistor logic (DTL) circuits introduced saturating bipo-

lar logic circuits and their characteristics.

• The input transistor of the transistor–transistor logic (TTL) circuit is driven

between saturation and the inverse active mode. This transistor reduces the

switching time by quickly pulling charge out of the base of a saturated transis-

tor. The totem-pole output stage was introduced in order to increase the

switching speed of the output stage.

• The Schottky clamped transistor has a Schottky diode between the base and col-

lector of an npn transistor, thus preventing the transistor from being driven deep

into saturation. The propagation delay time of Schottky TTL, then, is shorter

than that of regular TTL.

• Low-power Schottky TTL has the same basic conﬁguration as the DTL circuit.

Resistor values are increased so as to reduce the currents, which in turn reduce

the power dissipated per circuit.

• BiCMOS circuits incorporate the best characteristics of both the CMOS and

bipolar technologies. One example is a basic CMOS inverter that drives a bipo-

lar output stage. The high input impedance and low power dissipation of the

CMOS design is coupled with the high current drive capability of a bipolar out-

put stage. An example of a BiCMOS NOR logic circuit was considered.

• As an application, a static ECL logic gate to implement a speciﬁc logic function

was designed.

CHECKPOINT

After studying this chapter, the reader should have the ability to:

✓ Analyze and design a basic ECL OR/NOR logic gate.

✓ Analyze and design modiﬁed, lower-power ECL logic gates.

✓ Describe the operation and characteristics of the input transistor of a TTL logic

circuit.

✓ Analyze and design a TTL NAND logic gate.

✓ Describe the operation and characteristics of a Schottky transistor, and analyze

and design a Schottky TTL logic circuit.

✓ Analyze and design low-power Schottky TTL circuits, and explain tradeoffs

between power and switching speed.

REVIEW QUESTIONS

1. Sketch the circuit conﬁguration and discuss the operation of the basic ECL circuit.

2. Why must emitter-follower output stages be added to the diff-amp to make this

circuit a practical logic gate?

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Chapter 17 Bipolar Digital Circuits 1301

3. Sketch a modiﬁed ECL circuit in which a Schottky diode is incorporated in the

collector portion of the circuit. Explain the purpose of the Schottky diode.

4. Explain the concept of series gating for ECL circuits. What are the advantages

of this conﬁguration?

5. Sketch a diode–transistor NAND circuit and explain the operation of the circuit.

Explain the concept of minimum

and the purpose of the pull-down resistor.

6. Explain the operation and purpose of the input transistor in a TTL circuit.

7. Sketch a basic TTL NAND circuit and explain its operation.

8. Sketch a totem-pole output stage and explain its operation and the advantages of

incorporating this circuit in the TTL circuit.

9. Explain how maximum fanout can be based on maintaining the output transistor

in saturation when the output is low.

10. Explain how maximum fanout can be based on a maximum rated collector

current in the output transistor when the output is low.

11. Explain the operation of a Schottky clamped transistor. What are its advantages?

12. What is the primary advantage of a Schottky TTL NAND gate compared to a

regular TTL NAND gate.

13. Sketch a low-power Schottky TTL NAND circuit. What are the primary differences

between this circuit and the regular DTL circuit considered earlier in the chapter?

14. Sketch a basic BiCMOS inverter and explain its operation. Explain the advan-

tages of this inverter compared to a simple CMOS inverter.

PROBLEMS

[Note: In the following ECL and modiﬁed ECL problems, assume

(on) =

(on) = 0.7

V and

T = 300

K unless otherwise stated.

For the TTL problems and Schottky TTL problems, assume transistor and diode

parameters listed in Table 17.3. Also assume

= 0.3

V for a Schottky diode.]

Section 17.1 Emitter-Coupled Logic (ECL)

17.1 For the differential ampliﬁer circuit in Figure P17.1, neglect the base cur-

rents. (a) Determine

such that

= v

=−0.2

V when

=−0.7

(b) Using the results of part (a), ﬁnd

and

when (i)

=−1.0

V and

(ii)

=−0.4

V. (c) Using the results of part (a), determine the power dis-

sipated in the circuit for (i)

=−1.0

V and (ii)

=−0.4

–

REF

= –1.8 V

– 0.7 V

0.2 mA

Figure P17.1

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1302 Part 3 Digital Electronics

17.2 Neglect base currents in the circuit in Figure P17.2. (a) Determine

and

such that

= 80 μ

A and

= v

=−0.25

V when

=−1.0

(b) Using the results of part (a), determine

and

when (i)

−1.3

V and (ii)

=−0.7

V. (c) Using the results of part (a), determine the

power dissipation in the circuit for (i)

=−1.3

V and (ii)

=−0.7

–

= –2.5 V

REF

–1.0 V

Figure P17.2

= 0.5 mA

–3 V

+3 V

Figure P17.3

= –1.2 V

–5.2 V

2.5 kΩ

3 kΩ

Figure P17.5

17.3 Neglect base currents in the circuit in Figure P17.3. (a) Determine the value

such that the minimum value of

= 0

. (b) Determine the value of

such that

= 1V

when

= 1V

. (c) Determine the value of

= 0.40 mA

and

= 0.10 mA

17.4 For the circuit in Figure P17.3,

= R

= 1k

. Determine

and

for (a)

= 0.5V

and (b)

=−0.5

V. Neglect base currents.

17.5 Consider the circuit in Figure P17.5. (a) Determine

such that

−1 V when

is on and

is off. (b) For

=−0.7

, determine

such

that

=−1

V. (c) For

=−0.7

V, ﬁnd

and

, and for

−1.7 V, ﬁnd

and

. (d) Find the power dissipated in the circuit for

(i)

=−0.7

V and for (ii)

=−1.7

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Chapter 17 Bipolar Digital Circuits 1303

17.6 Consider the ECL logic circuit in Figure P17.6. Neglect base currents.

(a) Determine the reference voltage

. (b) Find the logic 0 and logic 1

voltage values at each output

and

. Assume that inputs

and

have the same values as the logic levels at

and

0.21 kΩ

0.24 kΩ

= 3.7 V

0.67 kΩ

0.80 kΩ

1.7 kΩ

1.33 kΩ

1.7 kΩ

Figure P17.6

= 0.7 V

–

= –2.1 V

–0.35 V

REF

Figure P17.7

17.7 Consider the circuit in Figure P17.7. (a) Determine

such that

REF

= 0.20

mA. (b) Determine the values of

and

such that the max-

imum currents in

and

are 0.12 mA. (c) Consider

A = B = 0

. What

? Using the results of part (a), ﬁnd

so that

=−0.7

V. (d) Con-

sider

A = B =−0.7

V. What is

? Using the results of part (a), ﬁnd

so that

=−0.7

17.8 Consider the circuit in Figure P17.8. Neglect base currents. Determine all

resistor values such that the following speciﬁcations are satisﬁed: logic

1 = 0

V and logic

0 =−1.0

is the average of the logic 1 and logic 0

values;

= 0.4

mA when

is on;

= i

= 0.4

mA;

= 0.8

mA when

logic 1; and

= 0.8

mA when

NOR

logic 1.

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1304 Part 3 Digital Electronics

= 1.5 V

+2.5 V

Figure P17.9

2.5 kΩ

18 kΩ

AB D

+ 5 V

Figure P17.10

–3 V

NOR

+0.7 V

Figure P17.8

17.9 In the ECL circuit in Figure P17.9, the outputs have a logic swing of 0.60 V,

which is symmetrical about the reference voltage. Neglect base currents.

The maximum emitter current for all transistors is 0.8 mA. Assume the

input logic voltages

are compatible with the output logic voltage. Deter-

mine all resistor values.

17.10 For the circuit in Figure P17.10, complete the following table. What logic

function does the circuit perform?

ABCDI

0000

5 V000

5 V 0 5 V 0

5 V5 V5 V5 V

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Chapter 17 Bipolar Digital Circuits 1305

17.11 Consider the ECL circuit in Figure P17.11. The input voltages A and B are

compatible with the output voltages

and

. (a) Determine the refer-

ence voltage

. (b) Determine the logic 0 and logic 1 levels at the outputs

and

. (c) Determine the voltage

for

A = B = logic 0

and for

A = B =

logic 1. (d) Determine the total power dissipated in the circuit

for

A = B = logic 0

and for

A = B = logic 1

1.5 kΩ1.5 kΩ

1 kΩ

2 kΩ2 kΩ

I =

1 mA

I =

1 mA

I =

1 mA

–5.2 V

Figure P17.11

0.8 kΩ

= 1.2 kΩ

2.6 kΩ

+5 V

+1.6 V

Figure P17.12

17.12 A positive-voltage-supply ECL logic gate is shown in Figure P17.12.

Neglect base currents. (a) What logic function is performed by this circuit.

(b) What are the logic 1 and logic 0 values of

at the output? (c) When

= logic 0

for one of the three inputs, determine

, and

(d) Repeat part (c) when

= logic 1

for all three inputs.

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1306 Part 3 Digital Electronics

Section 17.2 Modiﬁed ECL Circuit Conﬁgurations

17.13 In the circuit in Figure P17.13, the input voltages

and

are compatible

with the output voltages

and

. Neglect base currents. (a) Design an

appropriate value of

. State the reason for your selection. (b) Determine

the value of

such that, when

is on, the current in

is one-half that

. (c) Determine the value of

such that, when

is on, the current

is one-half that in

. (d) Calculate the power dissipated in the cir-

cuit when

= v

logic 0.

+0.9 V

3.3 kΩ

= 3.3 kΩ

–3.10 V

Figure P17.14

= 8 kΩ

= 12 kΩ

= 3.5 V

Figure P17.13

17.14 Consider the circuit in Figure P17.14. Neglect base currents. (a) What are

the logic 1 and logic 0 values at the output terminals

and

?. (b) For

= v

logic 0, determine

such that

= 0.25

mA. (c) Using the re-

sults of part (b), determine

such that

= 2i

when

is conducting.

(d) For

= v

logic 1 and

= R

, determine

, and

. (e) For

logic 0 and

logic 1, calculate the power dissipation in the circuit.

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Chapter 17 Bipolar Digital Circuits 1307

17.16 Assume the inputs

, and

to the circuit in Figure P17.16 are either

0 or 2.5 V. Let the B–E turn-on voltage be 0.7 V for both the npn and pnp

transistors. Assume

β = 150

for the npn devices and

β = 90

for the pnp

devices. (a) Determine the voltage at

for: (i)

A = B = C = D = 0

;

(ii)

A = B = 0

C = D = 2.5

V; and (iii)

A = C = 2.5

B = D = 0

(b) What logic function does this circuit implement? (c) Determine the

power dissipated in the circuit for the conditions given in part (a).

0.5 kΩ

–0.2 V

–

0.2 V

15 kΩ

2 kΩ

1 kΩ

15 kΩ

–3 V

–0.9 V

Figure P17.15

A B

= 15 kΩ

2 kΩ

= 2.5 V

Figure P17.16

17.15 For the circuit in Figure P17.15, assume transistor and diode parameters of

(on) = 0.7V

and

= 0.4

V. Neglect base currents. Find

, and

for: (a)

= v

=−0.4

V, (b)

= 0

=−0.4

V, (c)

−0.4

= 0

, (d)

= v

= 0

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