Neamen D. Microelectronics: Circuit Analysis and Design

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168 Part 1 Semiconductor Devices and Basic Applications

Solution: For

= V

= 0

, both M

and M

are cut off and

= V

= 5V

. For

= 5V

and

= 0

, the transistor M

is biased in the nonsaturation region, and we

can write

= I

5 − V

= K



2(V

− V



Solving for the output voltage V

, we obtain

= 0.29 V

The currents are

= I

5 − 0.29

= 0.236 mA

For

= 0

and

= 5V

, we have

= 0.29 V

and

= I

= 0.236 mA

When both inputs go high to

= V

= 5V

, we have

= I

+ I

,or

5 − V

= K



2(V

− V



+ K



2(V

− V



which can be solved for V

to yield

= 0.147 V

The currents are

5 − 0.147

= 0.243 mA

and

= I

= 0.121 mA

Comment: When either transistor is biased on, it is biased in the nonsaturation

region, since

< V

(sat)

, and the output voltage reaches a low state.

EXERCISE PROBLEM

Ex 3.13: For the circuit in Figure 3.46, assume the circuit and transistor parame-

ters are:

= 30 k

= 1V

, and

= 50 μA/V

. Determine V

, I

and I

for: (a)

= 5V

= 0

; and (b)

= V

= 5V

. (Ans. (a)

= 0.40 V

= I

= 0.153 mA

= 0

(b)

= 0.205 V

= 0.16 mA

= I

0.080 mA

)

This example and discussion illustrates that MOS transistors can be conﬁgured

in a circuit to perform logic functions. A more detailed analysis and design of

MOSFET logic gates and circuits is presented in Chapter 16. As we will see in that

chapter, most MOS logic gate circuits are fabricated by using CMOS, which means

designing circuits with both n-channel and p-channel transistors and no resistors.

MOSFET Small-Signal Ampliﬁer

The MOSFET, in conjunction with other circuit elements, can amplify small time-

varying signals. Figure 3.47(a) shows the MOSFET small-signal ampliﬁer, which is

a common-source circuit in which a time-varying signal is coupled to the gate

through a coupling capacitor. Figure 3.47(b) shows the transistor characteristics and

the load line. The load line is determined for

= 0

3.3.3

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Chapter 3 The Field-Effect Transistor 169

We can establish a particular Q-point on the load line by designing the ratio of

the bias resistors

and

. If we assume that

= V

sin ωt

, the gate-to-source volt-

age will have a sinusoidal signal superimposed on the dc quiescent value. As

the gate-to-source voltage changes over time, the Q-point will move up and down the

line, as indicated in the ﬁgure.

Moving up and down the load line translates into a sinusoidal variation in the

drain current and in the drain-to-source voltage. The variation in output voltage can

be larger than the input signal voltage, which means the input signal is ampliﬁed. The

actual signal gain depends on both the transistor parameters and the circuit element

values.

In the next chapter, we will develop an equivalent circuit for the transistor used

to determine the time-varying small-signal gain and other characteristics of the

circuit.

Test Your Understanding

TYU 3.12 The circuit shown in Figure 3.45 is biased at

= 10

V, and the transistor

parameters are

= 0.7

V and

= 4

mA/V

. Design the value of

such that the

output voltage will be

= 0.20

V when

= 10

V. (Ans. 0.666 k

)

TYU 3.13 The transistor in the circuit shown in Figure 3.48 has parameters

4 mA/V

and

= 0.8

V, and is used to switch the LED on and off. The LED

cutin voltage is

= 1.5

V. The LED is turned on by applying an input voltage

= 5

V. (a) Determine the value of R such that the diode current is 12 mA.

(b) From the results of part (a), what is the value of

? (Ans. (a)

R = 261 

(b)

= 0.374

TYU 3.14 In the circuit in Figure 3.46, let

= 25



and

= 1

V. (a) Deter-

mine the value of the conduction parameter

required such that

= 0.10

V when

= 0

and

= 5

V. (b) Using the results of part (a), ﬁnd the value of

when

= V

= 5

V. (Ans. (a)

= 0.248

mA/V

, (b)

= 0.0502

–

DSQ

GSQ

(sat)

–

(a) (b)

–

Figure 3.47 (a) An NMOS common-source circuit with a time-varying signal coupled to the

gate and (b) transistor characteristics, load line, and superimposed sinusoidal signals

LED

Figure 3.48

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170 Part 1 Semiconductor Devices and Basic Applications

3.4 CONSTANT-CURRENT BIASING

Objective: • Investigate current biasing of MOSFET devices.

As was shown in Figure 3.32, a MOSFET can be biased with a constant-current

source

. The gate-to-source voltage of the transistor in this circuit then adjusts

itself to correspond to the current

We can implement the current source by using MOSFET devices. The circuits

shown in Figures 3.49(a) and 3.49(b) are a ﬁrst step toward this design. The transis-

tors

and

in Figure 3.49(a) form a current mirror and are used to bias the

NMOS transistor

. Similarly, the transistors

and

in Figure 3.49(b) form a

current mirror and are used to bias the PMOS transistor

GS3

GS2

GS1

DS1

SDA

SGB

SGC

–

REF1

REF2

= 8 kΩ

–

––

–

SGA

–

(a) (b)

Figure 3.49 (a) NMOS current mirror and (b) PMOS current mirror

The operation and characteristics of these circuits are demonstrated in the

following two examples.

EXAMPLE 3.14

Objective: Analyze the circuit shown in Figure 3.49(a). Determine the bias current

the gate-to-source voltages of the transistors, and the drain-to-source voltage of

Assume circuit parameters of

REF1

= 200 μ

= 2.5

V, and

−

=−2.5

Assume transistor parameters of

= 0.4

V (all transistors),

λ = 0

(all transis-

tors),

= 0.25

mA/V

, and

= K

= 0.15

mA/V

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Chapter 3 The Field-Effect Transistor 171

Solution:

The drain current in

= I

REF1

= 200 μ

A and is given by the re-

lation

= K

GS3

− V

)

(the transistor is biased in the saturation region).

Solving for the gate-to-source voltage, we ﬁnd

GS3



+ V



0.2

0.15

+0.4

GS3

= 1.555 V

We note that

GS3

= V

GS2

= 1.555

V. We can write

= I

= K

GS2

− V

)

= 0.15(1.555 −0.4)

= 200 μA

The gate-to-source voltage

GS1

(assuming

is biased in the saturation region) can

be written as

GS1



+ V



0.2

0.25

+0.4

GS1

= 1.29 V

The drain-to-source voltage is found from

DS1

= V

− I

−(−V

GS1

)

= 2.5 −(0.2)(8) −(−1.29)

DS1

= 2.19 V

We may note that

is indeed biased in the saturation region.

Comment: Since the current mirror transistors

and

are matched (identical

parameters) and since the gate-to-source voltages are the same in the two transistors,

the bias current,

, is equal to (i.e., mirrors) the reference current,

REF1

EXERCISE PROBLEM

Ex 3.14: For the circuit shown in Figure 3.49(a), assume circuit parameters of

REF1

= 120 μ

= 3

V, and

−

=−3

V; and assume transistor parameters

= 0.4

λ = 0

= 50 μ

A/V

= 30 μ

A/V

, and

= 60

A/V

. Determine

and all gate-to source voltages. (Ans.

= 60 μ

GS1

= 1.495

GS2

= V

GS3

= 1.814

We will now consider a current mirror in which the bias current and reference current

are not equal.

EXAMPLE 3.15

Objective: Design the circuit shown in Figure 3.49(b) to provide a bias current of

= 150 μ

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172 Part 1 Semiconductor Devices and Basic Applications

Assume circuit parameters of I

REF2

= 250

= 3

V, and

−

=−3

V. As-

sume transistor parameters of

=−0.6

V (all transistors),

λ = 0

(all transistors),



= 40 μ

A/V

(all transistors),

W/L

= 15

, and

W/L

= 25

Solution: Since the bias current

and reference current I

REF2

are not equal, the

W/L

ratios of the current mirror transistors, M

and M

, will not be the same.

For M

, since the transistor is biased in the saturation region, we have

= I

REF2







SGC

+ V

)

250 =

(15)[V

SGC

+(−0.6)]

= 300(V

SGC

−0.6)

Then

SGC



250

300

+0.6

SGC

= 1.513 V

Since

SGC

= V

SGB

= 1.513

V, we obtain

= I







SGB

+ V

)

150 =





[1.513 + (−0.6)]

We ﬁnd





= 9

For M

, we have

= I







SGA

+ V

)

150 =

(25)(V

SGA

+(−0.6))

= 500(V

SGA

−0.6)

Now

SGA



150

500

+0.6

SGA

= 1.148 V

The source-to-drain voltage of M

is found from

SDA

= V

SGA

− I

− V

−

= 1.148 −(0.15)(8) − (−3)

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Chapter 3 The Field-Effect Transistor 173

SDA

= 2.95 V

We may note that the transistor M

is biased in the saturation region.

Comment: By designing the

W/L

ratios of the current mirror transistors, we can

obtain different reference current and bias current values.

EXERCISE PROBLEM

Ex 3.15: Consider the circuit shown in Figure 3.49(b). Assume circuit parameters

of I

REF2

= 0.1 mA,

= 5

V, and

−

=−5

V. The transistor parameters are

the same as given in Example 3.l5. Design the circuit such that

= 0.2

mA.

Also determine all source-to-gate voltages. (Ans.

SGC

= V

SGB

= 1.18

(W/L)

= 30

SGA

= 1.23

The constant-current source can be implemented by using MOSFETs as shown

in Figure 3.50. The transistors M

, M

, and M

form the current source. Transistors

and M

are each connected in a diode-type conﬁguration, and they establish a ref-

erence current. We noted in the last section that this diode-type connection implies

the transistor is always biased in the saturation region. Transistors M

and M

are

therefore biased in the saturation region, and M

is assumed to be biased in the satu-

ration region. The resulting gate-to-source voltage on M

is applied to M

, and this

establishes the bias current I

Since the reference current is the same in transistors M

and M

, we can write

GS3

− V

TN3

)

= K

GS4

− V

TN4

)

(3.28)

We also know that

GS4

+ V

GS3

= (−V

−

)

(3.29)

= 5 V

–

= –5 V

REF

–

DS1

DS2

GS1

++++

–

GS2

GS3

GS4

Figure 3.50 Implementation of a MOSFET constant-current source

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174 Part 1 Semiconductor Devices and Basic Applications

Solving Equation (3.29) for

GS4

and substituting the result into Equation (3.28)

yields

GS3



[(−V

−

) − V

TN4

] + V

TN3

1 +



(3.30)

Since

GS3

= V

GS2

, the bias current is

= K

GS3

− V

TN2

)

(3.31)

EXAMPLE 3.16

Objective: Determine the currents and voltages in a MOSFET constant-current

source.

For the circuit shown in Figure 3.50, the transistor parameters are:

0.2 mA/V

= K

= 0.1

mA/V

, and

TN1

= V

TN2

= V

TN3

= V

TN4

1V.

Solution: From Equation (3.30), we can determine

GS3

, as follows:

GS3



0.1

[5 − 1] +1

1 +



0.1

= 2.5V

Since M

and M

are identical transistors,

GS3

should be one-half of the bias volt-

age. The bias current I

is then

= (0.1) · (2.5 −1)

= 0.225 mA

The gate-to-source voltage on M

is found from

= K

GS1

− V

TN1

)

0.225 = (0.2) · (V

GS1

−1)

which yields

GS1

= 2.06 V

The drain-to-source voltage on M

DS2

= (−V

−

) − V

GS1

= 5 −2.06 = 2.94 V

Since

DS2

= 2.94 V > V

(sat) = V

GS2

− V

TN2

= 2.5 −1 = 1.5V

is biased

in the saturation region.

Design Consideration: Since in this example

and

are identical transistors,

the reference current I

REF

and bias current

are equal. By redesigning the width-to-

length ratios of

, and

, we can obtain a speciﬁc bias current

. If

and

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Chapter 3 The Field-Effect Transistor 175

are not identical, then

and

REF

will not be equal. A variety of design options

are possible with such a circuit conﬁguration.

EXERCISE PROBLEM

Ex 3.16: Consider the constant-current source shown in Figure 3.50. Assume

that the threshold voltage of each transistor is

= 1

V. (a) Design the ratio

such that

GS3

= 2

V. (b) Determine

such that

= 100 μ

and

such that

REF

= 200 μ

A. (Ans. (a)

(b)

= 0.1

mA/V

(c)

= 0.2

mA/V

= 0.05

mA/V

)

Test Your Understanding

TYU 3.15 Consider the circuit in Figure 3.49(b). Assume circuit parameters of

REF2

= 40 μ

= 2.5

−

=−2.5

V, and

= 20



. The transistor para-

meters are

=−0.30

= 40 μ

A/V

= 60 μ

A/V

, and

75 μ

A/V

. Determine

and all source-to-gate voltages. (Ans.

= 60 μ

SGC

= V

SGB

= 1.30

SGA

= 1.19

TYU 3.16 Consider the circuit shown in Figure 3.50. Assume all transistor threshold

voltages are 0.7 V. Determine the values of

, and

such that

REF

= 80 μ

= 120 μA

GS3

= 2

V, and

GS1

= 1.5

V. (Ans.

= 187.5

A/V

= 71.0 μ

A/V

= 47.3 μ

A/V

= 15.12 μ

A/V

)

3.5 MULTISTAGE MOSFET CIRCUITS

Objective: • Consider the dc biasing of multistage or multitransistor

circuits.

In most applications, a single-transistor ampliﬁer will not be able to meet the

combined speciﬁcations of a given ampliﬁcation factor, input resistance, and output

resistance. For example, the required voltage gain may exceed that which can be

obtained in a single-transistor circuit.

Transistor ampliﬁer circuits can be connected in series, or cascaded, as shown

in Figure 3.51. This may be done either to increase the overall small-signal voltage

gain, or provide an overall voltage gain greater than 1, with a very low output resistance.

–

Stage 1

Stage 2

Figure 3.51 Generalized two-stage ampliﬁer

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176 Part 1 Semiconductor Devices and Basic Applications

The overall voltage gain may not simply be the product of the individual ampliﬁca-

tion factors. Loading effects, in general, need to be taken into account.

There are many possible multistage conﬁgurations; we will examine a few here,

in order to understand the type of analysis required.

Multitransistor Circuit: Cascade Conﬁguration

The circuit shown in Figure 3.52 is a cascade of a common-source ampliﬁer followed

by a source-follower ampliﬁer. We will show in the next chapter that the common-

source ampliﬁer provides a small-signal voltage gain and the source-follower has a

low output impedance.

3.5.1

= 4 kΩ

= 5 V

–

= –5 V

–

Figure 3.52 Common-source ampliﬁer in cascade with source follower

DESIGN EXAMPLE 3.17

Objective: Design the biasing of a multistage MOSFET circuit to meet speciﬁc

requirements.

Consider the circuit shown in Figure 3.52 with transistor parameters

= 500 μ

A/V

= 200 μ

A/V

TN1

= V

TN2

= 1.2

V, and

= λ

= 0

Design the circuit such that

DQ1

= 0.2

mA,

DQ2

= 0.5

mA,

DSQ1

= V

DSQ2

, and

= 100



. Let

= 4



Solution: For output transistor M

, we have

DSQ2

= 5 −(−5) − I

DQ2

6 = 10 −(0.5)R

which yields

= 8k

. Also, assuming transistors are biased in the saturation

region,

DQ2

= K

GS2

− V

TN2

)

0.5 = 0.2(V

GS2

−1.2)

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Chapter 3 The Field-Effect Transistor 177

which yields

GS2

= 2.78 V

Since

DSQ2

= 6

V, the source voltage of

=−1V

. With

GS2

2.78 V

, the gate voltage on

must be

=−1 + 2.78 = 1.78 V

The resistor

is then

5 − 1.78

0.2

= 16.1k

For

DSQ1

= 6

V, the source voltage of

= 1.78 −6 =−4.22 V

The resistor

is then

−4.22 − (−5)

0.2

= 3.9k

For transistor

, we have

DQ1

= K

GS1

− V

TN1

)

0.2 = 0.50(V

GS1

−1.2)

which yields

GS1

= 1.83 V

To ﬁnd

and

, we can write

GS1



+ R



(10) − I

DQ1

Since

+ R



+ R



· R

then, since the input resistance is speciﬁed to be 100 k



, we have

1.83 =

(100)(10) − (0.2)(3.9)

which yields

= 383



. From

= 100



, we ﬁnd that

= 135



Comment: Both transistors are biased in the saturation region, as assumed, which is

desired for linear ampliﬁers as we will see in the next chapter.

EXERCISE PROBLEM

Ex 3.17: The transistor parameters for the circuit shown in Figure 3.52 are the

same as described in Example 3.17. Design the circuit such that

DQ1

= 0.1

mA,

DQ2

= 0.3

mA,

DSQ1

= V

DSQ2

= 5

V, and

= 200



. (Ans.

16.7k

= 25.8



= 24.3



= 491



, and

= 337



)

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