Neamen D. Microelectronics: Circuit Analysis and Design

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198 Part 1 Semiconductor Devices and Basic Applications

3.33 Consider the circuit shown in Figure P3.33. The transistor parameters are

= 0.4

V and



= 120 μ

A/V

. The voltage drop across

is to be

0.20 V. Design the transistor

W/L

ratio such that

= V

(

sat

)

+0.4

and determine

and

such that

= 200



= 1.8 V

4 kΩ

1 kΩ

= 1.8 V

2 kΩ

Figure P3.33 Figure P3.34

3.34 The transistor parameters for the transistor in Figure P3.34 are

= 0.4



= 120 μ

A/V

, and

W/L = 50

. (a) Determine

such

that

= 0.35

mA. (b) Determine

and

(

sat

)

3.35 For the transistor in the circuit in Figure P3.35, the parameters are

= 0.4



= 120 μ

A/V

, and

W/L = 25

. Determine

, and

. Sketch the load line and plot the

-point.

D3.36 Design a MOSFET circuit with the conﬁguration shown in Figure P3.30.

The transistor parameters are

=−0.6



= 50 μ

A/V

, and

λ = 0

The circuit bias is

±3

V, the drain current is to be 0.2 mA, the drain-to-

source voltage is to be approximately 3 V, and the voltage across

is to be

approximately equal to

. In addition, the current through the bias resis-

tors is to be no more than 10 percent of the drain current. (Hint: choose a

reasonable value of width-to-length ratio for the transistor.)

3.37 The parameters of the transistors in Figures P3.37 (a) and (b) are

0.5 mA/V

= 1.2V

, and

λ = 0

. Determine

and

for each tran-

sistor when (i)

= 50 μA

and (ii)

= 1mA

+5 V

–5 V

1.2 kΩ

0.5 kΩ

= 14 kΩ

= 6 kΩ

Figure P3.35

+5 V

−5 V

(a)

+5 V

(b)

Figure P3.37

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Chapter 3 The Field-Effect Transistor 199

3.38 For the circuit in Figure P3.38, the transistor parameters are

= 0.6V

and

= 200

μA/V

. Determine

and

*3.39 (a) Design the circuit in Figure P3.39 such that

= 0.50 mA

and

1 V. The transistor parameters are

= 0.25

mA/V

and

= 1.4V

Sketch the load line and plot the Q-point. (b) Choose standard resistor

values that are closest to the ideal designed values. What are the resulting

Q-point values? (c) If the resistors in part (b) have tolerances of

±10

percent, determine the maximum and minimum values of

3.40 The PMOS transistor in Figure P3.40 has parameters

=−0.7



= 50 μ

A/V

L = 0.8 μ

m, and

λ = 0

. Determine the values of

and

such that

= 0.1

mA and

= 2.5

+9 V

−9 V

= 0.25 mA

= 24 kΩ

Figure P3.38

+5 V

–5 V

= 47 kΩ

Figure P3.39

= 9 V

Figure P3.40

+5 V

–5 V

= 2 kΩ

Figure P3.41

3.41 Design the circuit in Figure P3.41 so that

= 2.5V

. The current in the

bias resistors should be no more than 10 percent of the drain current. The

transistor parameters are

=+1.5V

and

= 0.5

mA/V

*3.42 (a) Design the circuit in Figure P3.42 such that

= 0.25 mA

and

=−2

V. The nominal transistor parameters are

=−1.2V



35 μ

A/V

, and

W/L = 15

. Sketch the load line and plot the Q-point.

(b) Determine the maximum and minimum Q-point values if the tolerance

of the



parameter is

±5

percent.

+5 V

–5 V

Figure P3.42

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200 Part 1 Semiconductor Devices and Basic Applications

3.43 The parameters of the transistor in the circuit in Figure P3.43 are

−1.75 V and

= 3

mA/V

. Design the circuit such that

= 5mA

= 6V

, and

= 80 k

3.44 For each transistor in the circuit in Figure P3.44,



= 120 μ

A/V

. Also for

W/L = 4

and

= 0.4

V, and for

W/L = 1

and

=−0.6

(a) Determine the input voltage such that both

and

are biased in the

saturation region. (b) Determine the region of operation of each transistor

and the output voltage

for: (i)

= 0.6

V and (ii)

= 1.5

+5 V

–10 V

–5 V

Figure P3.43

= 5 V

Figure P3.44

= 5 V

Figure P3.46

3.45 Consider the circuit in Figure P3.44. The transistor parameters for

are

= 0.4

V and



= 120 μ

A/V

, and for

are

=−0.6



= 120 μ

A/V

, and

W/L = 1

. Determine the

W/L

ratio of

such that

= 0.025

V when

= 3

3.46 The transistors in the circuit in Figure P3.46 both have parameters

= 0.4

V and



= 120 μ

A/V

. (a) If the width-to-length ratios of

and

are

(W/L)

= (W/L)

= 30

, determine

GS1

GS2

, and

(b) Repeat part (a) if the width-to-length ratios are changed to

(W/L)

= 30

and

(W/L)

= 15

. (c) Repeat part (a) if the width-to-length ratios are

changed to

(W/L)

= 15

and

(W/L)

= 30

3.47 Consider the circuit in Figure P3.47. (a) The nominal transistor parameters

are

= 0.6

V and



= 120 μ

A/V

. Design the width-to-length ratio re-

quired in each transistor such that

= 0.8

mA,

= 2.5

V, and

= 6

V. (b) Determine the change in the values of

and

if the



pa-

rameter in each transistor changes by (i)

percent and (ii)

−5

percent.

and

if the



parameter of

decreases

by 5 percent and the



parameter of

and

increases by 5 percent.

3.48 The transistors in the circuit in Figure 3.36 in the text have parameters

= 0.6



= 120 μ

A/V

, and

λ = 0

. The width-to-length ratio of

(W/L)

= 2

. Design the width-to-length ratio of the driver transistor

such that

= 0.15

V when

= 5V

3.49 For the circuit in Figure 3.39 in the text, the transistor parameters are:

TND

= 0.6

TNL

=−1.2

λ = 0

, and



= 120 μ

A/V

. Let

= 5

V. The width-to-length ratio of

(W/L)

= 2

. Design the

width-to-length ratio of the driver transistor such that

= 0.10

V when

= 5

= 9 V

Figure P3.47

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Chapter 3 The Field-Effect Transistor 201

Section 3.3 MOSFET Switch and Ampliﬁer

3.50 Consider the circuit in Figure P3.50. The circuit parameters are

= 3

and

= 30



. The transistor parameters are

= 0.4

V and



= 120 μ

A/V

. (a) Determine the transistor width-to-length ratio such

that

= 0.08

V when

= 2.6

V. (b) Repeat part (a) for

= 3

Figure P3.50

Light

outpu

+5 V

Figure P3.51

Light

LED

outpu

+5 V

Figure P3.52

3.51 The transistor in the circuit in Figure P3.51 is used to turn the LED on and

off. The transistor parameters are

= 0.6



= 80 μ

A/V

, and

λ = 0

The diode cut-in voltage is

= 1.6

V. Design

and the transistor width-

to-length ratio such that

= 12

mA for

= 5

V and

= 0.15

3.52 The circuit in Figure P3.52 is another conﬁguration used to switch an LED on

and off. The transistor parameters are

=−0.6



= 40 μ

A/V

, and

λ = 0

. The diode cut-in voltage is

= 1.6

V. Design

and the transistor

width-to-length ratio such that

= 15

mA for

= 0

V and

= 0.20

3.53 For the two-input NMOS NOR logic gate in Figure 3.46 in the text, the tran-

sistor parameters are

TN1

= V

TN2

= 0.6

= λ

= 0

, and



= k



120 μ

A/V

. The drain resistor is

= 50



. (a) Determine the width-to-

length ratios of the transistors so that

= 0.15 V

when

= V

= 5

Assume that

(W/L)

= (W/L)

. (b) Using the results of part (a), ﬁnd

when

= 5

V and

= 0.2

3.54 All transistors in the current-source circuit shown in Figure 3.49(a) in the

text have parameters

= 0.4



= 120 μ

A/V

, and

λ = 0

. Transistors

and

are matched. The bias sources are

= 2.5

V and

−

=−2.5

The currents are to be

= 125 μ

A and

REF1

= 225 μ

A. For

, we re-

quire

DS2

(

sat

)

= 0.5

V, and for

we require

DS1

= 2

V. (a) Find the

W/L

ratios of the transistors. (b) Find

3.55 All transistors in the current-source circuit shown in Figure 3.49(b) in the

text have parameters

=−0.4



= 50 μ

A/V

, and

λ = 0

. The bias

sources are

= 5V

and

−

=−5V

. The currents are to be

= 200 μ

A and

REF2

= 125 μA

. For

, we require

SDB

(sat) = 0.8V

and for

, we require

SDA

= 4

V. Transistors

and

are matched.

(a) Find the

W/L

ratios of the transistors. (b) Find the value of

3.56 Consider the circuit shown in Figure 3.50 in the text. The threshold voltage

and process conduction parameter for each transistor is

= 0.6

V and



= 120 μ

A/V

. Let

λ = 0

for all transistors. Assume that

and

are

matched. Design width-to-length ratios such that

= 0.35

mA,

REF

= 0.15

mA, and

DS2

(

sat

)

= 0.5

V. Find

such that

DS1

= 3.5

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202 Part 1 Semiconductor Devices and Basic Applications

Section 3.6 Junction Field-Effect Transistor

3.57 The gate and source of an n-channel depletion-mode JFET are connected

together. What value of V

will ensure that this two-terminal device is

biased in the saturation region. What is the drain current for this bias

condition?

3.58 For an n-channel JFET, the parameters are

DSS

= 6

mA and

=−3

Calculate V

(sat). If

> V

(sat), determine I

for: (a) V

= 0,

(b)

=−1

V, (c)

=−2

V, and (d)

=−3

3.59 A p-channel JFET biased in the saturation region with V

=5 V has a drain

current of

= 2.8

mA at

= 1

V and

= 0.30

mA at

= 3

Determine I

DSS

and V

3.60 Consider the p-channel JFET in Figure P3.60. Determine the range of V

that will bias the transistor in the saturation region. If

DSS

= 6

mA and

= 2.5

V, ﬁnd V

3.61 Consider a GaAs MESFET. When the device is biased in the saturation re-

gion, we ﬁnd that

= 18.5

μA at

= 0.35

V and

= 86.2

μA at

= 0.50

V. Determine the conduction parameter k and the threshold

voltage V

3.62 The threshold voltage of a GaAs MESFET is

= 0.24

V. The maximum

allowable gate-to-source voltage is V

= 0.75 V. When the transistor is bi-

ased in the saturation region, the maximum drain current is

= 250

μA.

What is the value of the conduction parameter k?

*3.63 For the transistor in the circuit in Figure P3.63, the parameters are:

DSS

10 mA and

=−5

V. Determine I

, V

GSQ

, and V

DSQ

3.64 Consider the source follower with the n-channel JFET in Figure P3.64. The

input resistance is to be R

=500 k



. We wish to have I

=5 mA, V

DSQ

8 V, and

GSQ

=−1

V. Determine R

, R

, and R

, and the required transis-

tor values of I

DSS

and V

3.65 The transistor in the circuit in Figure P3.65 has parameters

DSS

= 8

and

= 4

V. Design the circuit such that

= 5

mA. Assume R

100 k



. Determine V

and V

3.66 For the circuit in Figure P3.66, the transistor parameters are I

DSS

= 7 mA

and V

= 3 V. Let R

+ R

= 100 k



. Design the circuit such that I

5.0 mA and V

SDQ

= 6 V.

= 2 mA

Figure P3.60

= 20 V

= 50 kΩ

= 0.2 kΩ

= 2 kΩ

–

Figure P3.63

= 10 V

Figure P3.64

= 2 kΩ

= 20 V

= 0.5 kΩ

Figure P3.65

= 12 V

= 0.3 kΩ

Figure P3.66

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Chapter 3 The Field-Effect Transistor 203

3.67 The transistor in the circuit in Figure P3.67 has parameters I

DSS

=8 mA and

=−4

V. Determine V

, I

, V

GSQ

, and V

DSQ

3.68 Consider the circuit in Figure P3.68. The quiescent value of V

is found to

be V

DSQ

= 5 V. If I

DSS

= 10 mA, determine I

, V

GSQ

, and V

3.69 For the circuit in Figure P3.69, the transistor parameters are I

DSS

= 4 mA

and

=−3

V. Design R

such that

=|V

. What is the value of I

3.70 Consider the source-follower circuit in Figure P3.70. The transistor para-

meters are I

DSS

= 2 mA and V

= 2 V. Design the circuit such that I

1 mA, V

SDQ

= 10 V, and the current through R

and R

is 0.1 mA.

3.71 The GaAs MESFET in the circuit in Figure P3.71 has parameters k =

250 μA/V

and V

= 0.20 V. Let R

+ R

= 150 k



. Design the circuit

such that

= 40

μA and V

= 2 V.

3.72 For the circuit in Figure P3.72, the GaAs MESFET threshold voltage is

= 0.15

V. Let

= 50



. Determine the value of the conduction pa-

rameter required so that

= 0.70

V when

= 0.75

COMPUTER SIMULATION PROBLEMS

3.73 Using a computer simulation, verify the results of Exercise Ex 3.5.

3.74 (a) Using a computer simulation, plot the voltage transfer characteristics of

the CMOS circuit shown in Figure 3.41. Use the parameters given in Ex-

ample 3.11. (b) Repeat part (a) for the case when the width-to-length ratio

is doubled.

3.75 (a) Using a computer simulation, plot the voltage transfer characteristics of

the NMOS circuit shown in Figure 3.46 for

= 0

and

0 ≤ V

≤ 5

V. Use

the circuit and transistor parameters given in Example 3.13. (b) Repeat part

(a) for

0 ≤ V

= V

≤ 5

3.76 Using a computer simulation, verify the results of Example 3.17 for the

multitransistor circuit shown in Figure 3.52.

= 2 kΩ

= 140 kΩ

= 20 V

= 60 kΩ

= 2.7 kΩ

Figure P3.67

= 12 V

20 kΩ

= 2 kΩ

0.5 kΩ

= 1 kΩ

= 450 kΩ

–

Figure P3.68

= 10 V

Figure P3.69

= 20 V

Figure P3.70

= 3 V

= 10 kΩ

Figure P3.71

= 3 V

Figure P3.72

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204 Part 1 Semiconductor Devices and Basic Applications

DESIGN PROBLEMS

[Note: All design should be correlated with a computer simulation.]

*D3.77 Consider the PMOS circuit shown in Figure 3.30. The circuit is to be re-

designed such that

= 100 μ

A and the Q-point is in the center of the sat-

uration region of the load line. Assume

+ R

= 500



and assume the

same transistor parameters as given in Exercise Ex 3.6.

*D3.78 Consider the circuit in Figure 3.39 with a depletion load. Assume the circuit

is biased at

= 3.3

V, and assume transistor threshold voltages of

TND

= 0.4

V and

TNL

=−0.75

V. Also assume



= 80 μ

A/V

. Design

the circuit such that

= 0.05

V when

= 3.3

V and that the maximum

power dissipation is

150 μ

*D3.79 The constant-current source in Figure 3.50 is to be redesigned. The bias

voltages are

= 3.3

V and

−

=−3.3

V. The parameters of all transis-

tors are

= 0.4

V and



= 100 μ

A/V

. The currents are to be

REF

= 100 μ

A and

= 60 μ

A. We will also specify that

DS2

(

sat

)

0.6

GS1

= V

GS2

, and

DS1

= 2.5

V. Determine all width-to-length ratios

and the value of

. (Note: the minimum width-to-length ratio is to be

greater than one.)

*D3.80 Consider the multitransistor circuit in Figure 3.52. The bias voltages are

changed to

= 3.3

V and

−

=−3.3

V. The transistor parameters are

= 0.4

V and



= 100 μ

A/V

. Design the circuit such that

DQ1

100 μ

DQ2

= 250 μ

DSQ1

= V

DSQ2

= 3.3

V, and

= 200



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Chapter

In Chapter 3, we described the structure and operation of the FET, in particular the

MOSFET, and analyzed and designed the dc response of circuits containing these

devices. In this chapter, we emphasize the use of the FETs in linear ampliﬁer appli-

cations. Linear ampliﬁers imply that, for the most part, we are dealing with analog

signals. The magnitude of an analog signal may have any value, within limits, and

may vary continuously with respect to time. Although a major use of MOSFETs is in

digital applications, they are also used in linear ampliﬁer circuits.

We will begin to see how all-transistor circuits, that is, circuits with no resistors,

can be designed. Since MOS transistors are small devices, high-density all-transistor

circuits can be fabricated as integrated circuits.

PREVIEW

In this chapter, we will:

• Investigate the process by which a single-MOS transistor circuit can amplify

a small, time-varying input signal.

• Develop the small-signal models of the transistor that are used in the analysis

of linear ampliﬁers.

• Discuss the three basic transistor ampliﬁer conﬁgurations.

• Analyze the common-source, source-follower, and common-gate ampliﬁers,

and become familiar with the general characteristics of these circuits.

• Compare the general characteristics of the three basic ampliﬁer

conﬁgurations.

• Analyze all-MOS transistor circuits that become the foundation of integrated

circuits.

• Analyze multitransistor or multistage ampliﬁers and understand the advan-

tages of these circuits over single-transistor ampliﬁers.

• Develop the small-signal model of JFET devices and analyze basic JFET

ampliﬁers.

• As an application, incorporate MOS transistors in a design of a two-stage

ampliﬁer.

Basic FET Ampliﬁers

205

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206 Part 1 Semiconductor Devices and Basic Applications

4.1 THE MOSFET AMPLIFIER

Objective: • Investigate the process by which a single-transistor

circuit can amplify a small, time-varying input signal and develop the

small-signal models of the transistor that are used in the analysis of

linear ampliﬁers.

In this chapter, we will be considering signals, analog circuits, and ampliﬁers. A

signal contains some type of information. For example, sound waves produced by a

speaking human contain the information the person is conveying to another person.

A sound wave is an analog signal. The magnitude of an analog signal can take on

any value, within limits, and may vary continuously with time. Electronic circuits

that process analog signals are called analog circuits. One example of an analog cir-

cuit is a linear ampliﬁer. A linear ampliﬁer magniﬁes an input signal and produces

an output signal whose magnitude is larger and directly proportional to the input

signal.

In this chapter, we analyze and design linear ampliﬁers that use ﬁeld-effect tran-

sistors as the amplifying device. The term small signal means that we can linearize

the ac equivalent circuit. We will deﬁne what is meant by small signal in the case of

MOSFET circuits. The term linear ampliﬁers means that we can use superposition so

that the dc analysis and ac analysis of the circuits can be performed separately and

the total response is the sum of the two individual responses.

The mechanism with which MOSFET circuits amplify small time-varying

signals was introduced in the last chapter. In this section, we will expand that

discussion using the graphical technique, dc load line, and ac load line. In the

process, we will develop the various small-signal parameters of linear circuits and

the corresponding equivalent circuits.

Graphical Analysis, Load Lines,

and Small-Signal Parameters

Figure 4.1 shows an NMOS common-source circuit with a time-varying voltage

source in series with the dc source. We assume the time-varying input signal is sinu-

soidal. Figure 4.2 shows the transistor characteristics, dc load line, and Q-point,

where the dc load line and Q-point are functions of

, R

, and the transistor

parameters. For the output voltage to be a linear function of the input voltage, the

transistor must be biased in the saturation region. (Note that, although we primarily

use n-channel, enhancement-mode MOSFETs in our discussions, the same results

apply to the other MOSFETs.)

Also shown in Figure 4.2 are the sinusoidal variations in the gate-to-source volt-

age, drain current, and drain-to-source voltage, as a result of the sinusoidal source v

The total gate-to-source voltage is the sum of

GSQ

and

. As

increases, the

instantaneous value of

increases, and the bias point moves up the load line. A

larger value of

means a larger drain current and a smaller value of

. For a

negative

(the negative portion of the sine wave), the instantaneous value of

decreases below the quiescent value, and the bias point moves down the load line. A

smaller

value means a smaller drain current and increased value of

. Once the

4.1.1

–

GSQ

–

Figure 4.1 NMOS common-

source circuit with time-

varying signal source in

series with gate dc source

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Chapter 4 Basic FET Ampliﬁers 207

DSQ

GSQ

(sat)

Time

Q-point

Figure 4.2 Common-source transistor characteristics, dc load line, and sinusoidal variation

in gate-to-source voltage, drain current, and drain-to-source voltage

Q-point is established, we can develop a mathematical model for the sinusoidal, or

small-signal, variations in gate-to-source voltage, drain-to-source voltage, and drain

current.

The time-varying signal source

in Figure 4.1 generates a time-varying

component of the gate-to-source voltage. In this case,

= v

, where

is the time-

varying component of the gate-to-source voltage. For the FET to operate as a linear

ampliﬁer, the transistor must be biased in the saturation region, and the instantaneous

drain current and drain-to-source voltage must also be conﬁned to the saturation

region.

When symmetrical sinusoidal signals are applied to the input of an ampliﬁer,

symmetrical sinusoidal signals are generated at the output, as long as the ampliﬁer

operation remains linear. We can use the load line to determine the maximum output

symmetrical swing. If the output exceeds this limit, a portion of the output signal will

be clipped and signal distortion will occur.

In the case of FET ampliﬁers, the output signal must avoid cutoff (

= 0

) and

must stay in the saturation region (

(sat)). This maximum range of output

signal can be determined from the load line in Figure 4.2.

Transistor Parameters

We will be dealing with time-varying as well as dc currents and voltages in this

chapter. Table 4.1 gives a summary of notation that will be used. This notation was

Table 4.1 Summary of notation

Variable Meaning

, v

Total instantaneous values

, V

DC values

, v

Instantaneous ac values

, V

Phasor values

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