Neamen D. Microelectronics: Circuit Analysis and Design
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218 Part 1 Semiconductor Devices and Basic Applications
Since the source is at ground potential, there is no body effect. The output voltage
is
V
o
=−g
m
V
gs
(r
o
R
D
)
(4.27)
The input gate-to-source voltage is
V
gs
=
R
i
R
i
+ R
Si
· V
i
(4.28)
so the small-signal voltage gain is
A
v
=
V
o
V
i
=−g
m
(r
o
R
D
) ·
R
i
R
i
+ R
Si
(4.29)
We can also relate the ac drain current to the ac drain-to-source voltage, as
V
ds
=−I
d
(R
D
)
.
Figure 4.16 shows the dc load line, the transition point (that separates the satura-
tion bias region and nonsaturation bias region), and the Q-point, which is in the
saturation region. In order to provide the maximum symmetrical output voltage swing
and keep the transistor biased in the saturation region, the Q-point must be near the
middle of the saturation region. At the same time, the input signal must be small
enough for the amplifier to remain linear.
The input and output resistances of the amplifier can be determined from Fig-
ure 4.15. The input resistance to the amplifier is
R
i
= R
1
R
2
. Since the low-frequency
input resistance looking into the gate of the MOSFET is essentially infinite, the input
resistance is only a function of the bias resistors. The output resistance looking back
into the output terminals is found by setting the independent input source V
i
equal to
zero, which means that
V
gs
= 0
. The output resistance is therefore
R
o
= R
D
r
o
.
EXAMPLE 4.3
Objective: Determine the small-signal voltage gain and input and output resistances
of a common-source amplifier.
For the circuit shown in Figure 4.14, the parameters are:
V
DD
= 3.3
V,
R
D
= 10
k
,
R
1
= 140
k
,
R
2
= 60
k
, and
R
Si
= 4
k
. The transistor parameters
are:
V
TN
= 0.4
V,
K
n
= 0.5
mA/V
2
, and
λ = 0.02
V
−1
.
v
DS
I
DQ
V
DD
V
DSQ
V
DS
(sat) = V
GS
– V
TN
i
D
Q-point
Transition point
dc load line, slope = –
1
R
D
I
D
(max) =
V
DD
R
D
Figure 4.16 DC load line and transition point separating saturation and nonsaturation regions
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Chapter 4 Basic FET Amplifiers 219
Solution
(dc calculations): The dc or quiescent gate-to-source voltage is
V
GSQ
=
R
2
R
1
+ R
2
(V
DD
) =
60
140 + 60
(3.3) = 0.99 V
The quiescent drain current is
I
DQ
= K
n
(V
GSQ
− V
TN
)
2
= (0.5)(0.99 −0.4)
2
= 0.174
mA
and the quiescent drain-to-source voltage is
V
DSQ
= V
DD
− I
DQ
R
D
= 3.3 −
(
0.174)(10
)
= 1.56 V
Since
V
DSQ
> V
GSQ
− V
TN
, the transistor is biased in the saturation region.
Small-signal Voltage Gain: The small-signal transconductance g
m
is then
g
m
= 2
K
n
I
DQ
= 2
√
(0.5)(0.174) = 0.590
mA/V
and the small-signal output resistance is
r
o
=
1
λI
Q
=
1
(0.02)(0.174)
= 287 k
The input resistance to the amplifier is
R
i
= R
1
R
2
= 14060 = 42 k
From Figure 4.15 and Equation (4.29), the small-signal voltage gain is
A
v
=−g
m
(r
o
R
D
)
R
i
R
i
+ R
Si
=−(0.59)(28710)
42
42 + 4
or
A
v
=−5.21
Input and Output Resistances: As already calculated, the amplifier input resis-
tance is
R
i
= R
1
R
2
= 14060 = 42 k
and the amplifier output resistance is
R
o
= R
D
r
o
= 10287 = 9.66 k
Comment: The resulting
Q
-point is not in the center of the saturation region. There-
fore, this circuit does not achieve the maximum symmetrical output voltage swing in
this case.
Discussion: The small-signal input gate-to-source voltage is
V
gs
=
R
i
R
i
+ R
Si
· V
i
=
42
42 + 4
· V
i
= (0.913) · V
i
Since R
Si
is not zero, the amplifier input signal V
gs
is approximately 91 percent of
the signal voltage. This is called a loading effect. Even though the input resistance to
the gate of the transistor is essentially infinite, the bias resistors greatly influence the
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220 Part 1 Semiconductor Devices and Basic Applications
amplifier input resistance and loading effect. This loading effect can be eliminated
or minimized when current source biasing is considered.
EXERCISE PROBLEM
Ex 4.3: The parameters of the circuit shown in Figure 4.14 are
V
DD
= 5
V,
R
1
= 520 k
,
R
2
= 320 k
,
R
D
= 10
k, and
R
Si
= 0
. Assume transistor para-
meters of
V
TN
= 0.8
V,
K
n
= 0.20
mA/V
2
, and
λ = 0
. (a) Determine the small-
signal transistor parameters g
m
and r
o
. (b) Find the small-signal voltage gain.
(c) Calculate the input and output resistances R
i
and R
o
(see Figure 4.15). (Ans.
(a) g
m
= 0.442
mA/V,
r
o
=∞
; (b)
A
v
=−4.42
; (c)
R
i
= 198
k,
R
o
= R
D
=
10 k)
DESIGN EXAMPLE 4.4
Objective: Design the bias of a MOSFET circuit such that the Q-point is in the
middle of the saturation region. Determine the resulting small-signal voltage gain.
Specifications: The circuit to be designed has the configuration shown in
Figure 4.17. Let
R
1
R
2
= 100
k
. Design the circuit such that the Q-point is
I
DQ
= 2
mA and the Q-point is in the middle of the saturation region.
+
–
R
2
v
i
R
1
C
C
R
D
V
DD
= 12 V
I
D
= 2 mA
v
O
Figure 4.17 Common-source NMOS transistor circuit
Choices: A transistor with nominal parameters
V
TN
= 1
V,
k
n
= 80 μA/V
2
,
W/L = 25
, and
λ = 0.015 V
−1
is available.
Solution (dc design): The load line and the desired Q-point are given in Figure 4.18.
If the Q-point is to be in the middle of the saturation region, the current at the transi-
tion point must be 4 mA.
The conductivity parameter is
K
n
=
k
n
2
·
W
L
=
0.080
2
(25) = 1mA/V
2
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Chapter 4 Basic FET Amplifiers 221
V
DS
(sat) = V
GS
– V
TN
V
DSQ
= 7 V V
DD
= 12 VV
DSt
(sat)
V
GSQ
= 2.41 V
2 mA
4 mA
Load line, slope = –
1
R
D
v
DS
i
D
Q-point
Figure 4.18 DC load line and transition point for NMOS circuit shown in Figure 4.17
We can now calculate
V
DS
(sat) at the transition point. The subscript t indicates
transition point values. To determine
V
GSt
, we use
I
Dt
= 4 = K
n
(V
GSt
− V
TN
)
2
= 1(V
GSt
−1)
2
which yields
V
GSt
= 3V
Therefore
V
DSt
= V
GSt
− V
TN
= 3 −1 = 2V
If the Q-point is in the middle of the saturation region, then
V
DSQ
= 7
V, which
would yield a 10 V peak-to-peak symmetrical output voltage. From Figure 4.17, we
can write
V
DSQ
= V
DD
− I
DQ
R
D
or
R
D
=
V
DD
− V
DSQ
I
DQ
=
12 − 7
2
= 2.5k
We can determine the required quiescent gate-to-source voltage from the current
equation, as follows:
I
DQ
= 2 = K
n
(V
GSQ
− V
TN
)
2
= (1)(V
GSQ
−1)
2
or
V
GSQ
= 2.41 V
Then
V
GSQ
= 2.41 =
R
2
R
1
+ R
2
(V
DD
) =
1
R
1
R
1
R
2
R
1
+ R
2
(V
DD
)
=
R
i
R
1
· V
DD
=
(100)(12)
R
1
which yields
R
1
= 498 k and R
2
= 125 k
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222 Part 1 Semiconductor Devices and Basic Applications
Solution (ac analysis): The small-signal transistor parameters are
g
m
= 2
K
n
I
DQ
= 2
(1)(2) = 2.83 mA/V
and
r
o
=
1
λI
DQ
=
1
(0.015)(2)
= 33.3k
The small-signal equivalent circuit is the same as shown in Figure 4.7. The small-
signal voltage gain is
A
v
=
V
o
V
i
=−g
m
(
r
o
R
D
)
=−(2.83)(33.32.5)
or
A
v
=−6.58
Comment: Establishing the Q-point in the middle of the saturation region allows the
maximum symmetrical swing in the output voltage, while keeping the transistor
biased in the saturation region.
EXERCISE PROBLEM
Ex 4.4: Consider the circuit shown in Figure 4.14. Assume transistor parameters
of
V
TN
= 0.8
V,
K
n
= 0.20
mA/V
2
, and
λ = 0
. Let
V
DD
= 5
V,
R
i
= R
1
R
2
=
200 k, and
R
Si
= 0
. Design the circuit such that
I
DQ
= 0.5
mA and the Q-point
is in the center of the saturation region. Find the small-signal voltage gain.
(Ans.
R
D
= 2.76
k,
R
1
= 420
k,
R
2
= 382
k,
A
v
=−1.75
)
Common-Source Amplifier with Source Resistor
A source resistor R
S
tends to stabilize the Q-point against variations in transistor
parameters (Figure 4.19). If, for example, the value of the conduction parameter
varies from one transistor to another, the Q-point will not vary as much if a source
4.3.2
+
–
v
i
C
C
R
D
= 7 kΩ
+5 V
–5 V
R
1
= 165 kΩ
R
2
= 35 kΩ
v
O
R
S
= 0.5 kΩ
Figure 4.19 Common-source circuit with source resistor and positive and negative supply
voltages
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Chapter 4 Basic FET Amplifiers 223
resistor is included in the circuit. However, as shown in the following example, a
source resistor also reduces the signal gain.
The circuit in Figure 4.19 is an example of a situation in which the body effect
should be taken into account. The substrate (not shown) would normally be
connected to the
−5
V supply, so that the body and substrate terminals are not at the
same potential. However, in the following example, we will neglect this effect.
The circuit shown in Figure 4.20(a) is a PMOS version of the common-source
amplifier with a source resistor
R
S
included.
EXAMPLE 4.5
Objective: Determine the small-signal voltage gain of a PMOS transistor circuit.
Consider the circuit shown in Figure 4.20(a). The transistor parameters are
K
p
= 0.80
mA/V
2
,
V
TP
=−0.5
V, and
λ = 0
. The quiescent drain current is found
to be
I
DQ
= 0.297
mA.
The small-signal equivalent circuit is shown in Figure 4.20(b). To sketch the
small-signal equivalent circuit, start with the three terminals of the transistor, draw in
the transistor equivalent circuit between these three terminals, and then sketch in the
other circuit elements around the transistor.
Solution: The small-signal output voltage is
V
o
=+g
m
V
sg
R
D
Writing a KVL equation from the input around the gate–source loop, we find
V
i
=−V
sg
− g
m
V
sg
R
S
or
V
sg
=
−V
i
1 + g
m
R
S
Substituting this expression for V
sg
into the output voltage equation, we find the
small-signal voltage gain as
A
v
=
V
o
V
i
=
−g
m
R
D
1 + g
m
R
S
+
–
v
i
C
c
R
S
= 3 kΩ
+3 V
–3 V
R
1
= 100 kΩ
R
2
= 200 kΩ
v
o
R
D
= 10 kΩ
V
sg
V
o
g
m
V
sg
R
D
R
S
+
–
V
i
R
1
⎜⎜ R
2
+
–
S
G
D
(a) (b)
Figure 4.20 (a) PMOS circuit for Example 4.5, and (b) small-signal equivalent circuit
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224 Part 1 Semiconductor Devices and Basic Applications
The small-signal transconductance is
g
m
= 2
K
p
I
DQ
= 2
(0.80)(0.297) = 0.975 mA/V
We then find the small-signal voltage gain as
A
v
=
−(0.975)(10)
1 + (0.975)(3)
or
A
v
=−2.48
Comment: The analysis of a PMOS transistor circuit is essentially the same as that
of an NMOS transistor circuit. The voltage gain of a MOS transistor circuit that con-
tains a source resistor is degraded compared to a circuit without a source resistor.
However, the Q-point tends to be stabilized.
Discussion: We mentioned that including a source resistor tends to stabilize the
circuit characteristics against any changes in transistor parameters. If, for exam-
ple, the conduction parameter
K
p
varies by
±10
percent, we find the following
results.
K
p
(mA/V
2
) g
m
(mA/V) A
v
(V/V)
0.72 0.9121
−2.441
0.80 0.9749
−2.484
0.88 1.035
−2.521
With a
±10
percent variation in
K
p
, there is less than a
±1.8
percent variation in the
voltage gain.
EXERCISE PROBLEM
Ex 4.5: For the circuit shown in Figure 4.19, the transistor parameters are
V
TN
= 0.8
V,
K
n
= 1
mA/V
2
, and
λ = 0
. (a) From the dc analysis, find
I
DQ
and
V
DSQ
. (b) Determine the small-signal voltage gain. (Ans. (a)
I
DQ
= 0.494
mA,
V
DSQ
= 6.30
V; (b)
A
v
=−5.78)
.
Common-Source Circuit
with Source Bypass Capacitor
A source bypass capacitor added to the common-source circuit with a source resistor
will minimize the loss in the small-signal voltage gain, while maintaining the Q-
point stability. The Q-point stability can be further increased by replacing the source
resistor with a constant-current source. The resulting circuit is shown in Figure 4.21,
assuming an ideal signal source. If the signal frequency is sufficiently large so that
the bypass capacitor acts essentially as an ac short-circuit, the source will be held at
signal ground.
EXAMPLE 4.6
Objective: Determine the small-signal voltage gain of a circuit biased with a constant-
current source and incorporating a source bypass capacitor.
4.3.3
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Chapter 4 Basic FET Amplifiers 225
For the circuit shown in Figure 4.21, the transistor parameters are:
V
TN
= 0.8
V,
K
n
= 1
mA/V
2
, and
λ = 0
.
Solution: Since the dc gate current is zero, the dc voltage at the source terminal is
V
S
=−V
GSQ
, and the gate-to-source voltage is determined from
I
DQ
= I
Q
= K
n
(V
GSQ
− V
TN
)
2
or
0.5 = (1)(V
GSQ
−0.8)
2
which yields
V
GSQ
=−V
S
= 1.51 V
The quiescent drain-to-source voltage is
V
DSQ
= V
DD
− I
DQ
R
D
− V
S
= 5 −(0.5)(7) −(−1.51) = 3.01 V
The transistor is therefore biased in the saturation region.
The small-signal equivalent circuit is shown in Figure 4.22. The output voltage is
V
o
=−g
m
V
gs
R
D
R
D
= 7 kΩ
+5 V
–5 V
v
i
C
S
v
O
R
G
= 200 kΩ
I
Q
= 0.5 mA
+
–
Figure 4.21 NMOS common-source circuit with source bypass capacitor
V
gs
V
o
g
m
V
gs
–
+
V
i
R
G
R
D
= 7 kΩ
+
–
Flgure 4.22 Small-signal equivalent circuit, assuming the source bypass capacitor acts as a
short circuit
Since
V
gs
= V
i
, the small-signal voltage gain is
A
v
=
V
o
V
i
=−g
m
R
D
=−(1.414)(7) =−9.9
Comment: Comparing the small-signal voltage gain of 9.9 in this example to the
2.48 calculated in Example 4.5, we see that the magnitude of the gain increases when
a source bypass capacitor is included.
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226 Part 1 Semiconductor Devices and Basic Applications
EXERCISE PROBLEM
Ex 4.6: The common-source amplifier in Figure 4.23 has transistor parameters
k
p
= 40 μ
A/V
2
,
W/L = 40
,
V
TP
=−0.4
V, and
λ = 0.02
V
−1
. (a) Determine
I
DQ
and
V
SDQ
. (b) Find the small-signal voltage gain. (Ans. (a)
I
DQ
= 1.16
mA,
V
SDQ
= 2.29
V; (b)
A
v
=−3.68)
Test Your Understanding
TYU 4.6 Consider the common-source amplifier in Figure 4.24 with transistor
parameters
V
TN
= 1.8
V,
K
n
= 0.15
mA/V
2
, and
λ = 0
. (a) Calculate
I
DQ
and
V
DSQ
. (b) Determine the small-signal voltage gain. (c) Discuss the purpose of R
G
and
its effect on the small-signal operation of the amplifier. (Ans. (a)
I
DQ
= 1.05
mA,
V
DSQ
= 4.45
V; (b)
A
v
=−2.65
)
R
D
= 2 kΩ
+3 V
–3 V
v
i
C
S
C
C1
R
G
= 100 kΩ
R
S
= 1.2 kΩ
+
–
v
O
Figure 4.23 Figure for Exercise Ex 4.6
v
i
v
o
V
DD
= 15 V
+
–
C
C1
R
L
= 5 kΩ
R
D
= 10 kΩ
R
G
= 5 MΩ
C
C2
Figure 4.24 Figure for Exercise TYU 4.6
R
S
v
i
v
O
C
C
R
G
= 1 MΩ
+5 V
–5 V
R
D
+
–
C
S
Figure 4.25 Figure for Exercise TYU 4.7
TYU 4.7 The parameters of the transistor shown in Figure 4.25 are:
V
TP
=+0.8
V,
K
p
= 0.5
mA/V
2
, and
λ = 0.02 V
−1
. (a) Determine R
S
and R
D
such that
I
DQ
=
0.8 mA and
V
SDQ
= 3
V. (b) Find the small-signal voltage gain. (Ans. (a)
R
S
=
5.67 k,
R
D
= 3.08
k; (b)
A
v
=−3.71
)
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Chapter 4 Basic FET Amplifiers 227
4.4 THE COMMON-DRAIN
(SOURCE-FOLLOWER) AMPLIFIER
Objective: • Analyze the common-drain (source-follower) amplifier
and become familiar with the general characteristics of this circuit.
The second type of MOSFET amplifier to be considered is the common-drain
circuit. An example of this circuit configuration is shown in Figure 4.26. As seen in
the figure, the output signal is taken off the source with respect to ground and the drain
is connected directly to
V
DD
. Since
V
DD
becomes signal ground in the ac equivalent
circuit, we have the name common drain. The more common name is source follower.
The reason for this name will become apparent as we proceed through the analysis.
+
–
R
2
v
i
R
1
C
C
R
S
R
Si
V
DD
v
O
Flgure 4.26 NMOS source-follower or common-drain amplifier
(a) (b)
V
gs
V
o
V
in
g
m
V
gs
R
S
R
Si
–
+
r
o
V
i
R
1
⎪⎪ R
2
S
G
+
–
D
V
in
R
Si
R
i
V
gs
V
o
g
m
V
gs
R
S
–+
r
o
V
i
R
1
⎪⎪ R
2
+
–
Figure 4.27 (a) Small-signal equivalent circuit of NMOS source follower and (b) small-signal
equivalent circuit of NMOS source follower with all signal grounds at a common point
Small-Signal Voltage Gain
The dc analysis of the circuit is exactly the same as we have already seen, so we will
concentrate on the small-signal analysis. The small-signal equivalent circuit, assum-
ing the coupling capacitor acts as a short circuit, is shown in Figure 4.27(a). The
drain is at signal ground, and the small-signal resistance r
o
of the transistor is in
4.4.1
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