
Chapter 4 Basic FET Amplifiers 249
The small-signal voltage gain is then
A
v
=−g
m
(r
on
r
op
) =−(0.693)(500500) =−173
Comment: The voltage gain of the CMOS amplifier is on the same order of magni-
tude as the NMOS amplifier with depletion load. However, the CMOS amplifier does
not suffer from the body effect.
Discussion: In the circuit configuration shown in Figure 4.45(a), we must again
apply a dc voltage to the gate of M
1
to achieve the “proper” Q-point. We will show in
later chapters using more sophisticated circuits how the Q-point is more easily
established with current-source biasing. However, this circuit demonstrates the basic
principles of the CMOS common-source amplifier.
EXERCISE PROBLEM
Ex 4.13: For the circuit shown in Figure 4.45(a), assume transistor para-
meters of
V
TN
=+0.5
V,
V
TP
=−0.5
V,
k
n
= 80 μA/V
2
,
k
p
= 40 μA/V
2
, and
λ
n
= λ
p
= 0.015 V
−1
. Assume
I
Bias
= 0.1
mA. Assume M
2
and M
3
are matched.
Find the width-to-length ratio of M
1
such that the small-signal voltage gain is
A
v
=−250
. (Ans.
(W/L)
1
= 35.2
)
CMOS Source-Follower Amplifier
The same basic CMOS circuit configuration can be used to form a CMOS source-
follower amplifier. Figure 4.47(a) shows a source-follower circuit. We see that for
this source-follower circuit, the active load, which is M
2
, is an n-channel rather than
a p-channel device. The input signal is applied to the gate of M
1
and the output is at
the source of M
1
.
The small-signal equivalent circuit of this source-follower is shown in
Figure 4.47(b). This circuit, with two signal grounds, is redrawn as shown in
Figure 4.47(c) to combine the signal grounds.
EXAMPLE 4.14
Objective: Determine the small-signal voltage gain and output resistance of the
source-follower amplifier shown in Figure 4.47(a).
Assume the reference bias current is
I
Bias
= 0.20
mA and the bias voltage is
V
DD
= 3.3
V. Assume that all transistors are matched (identical) with parameters
V
TN
= 0.4
V,
K
n
= 0.20
mA/V
2
, and
λ = 0.01 V
−1
.
We may note that since M
3
and M
2
are matched transistors and have the same
gate-to-source voltages, the drain current in M
1
is
I
D1
= I
Bias
= 0.2
mA.
Solution (voltage gain): From Figure 4.47(c), we find the small-signal output volt-
age to be
V
o
= g
m1
V
gs
(r
o1
r
o2
)
A KVL equation around the outside loop produces
V
i
= V
gs
+ V
o
= V
gs
+ g
m1
V
gs
(r
o1
r
o2
)
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