Neamen D. Microelectronics: Circuit Analysis and Design

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438 Part 1 Semiconductor Devices and Basic Applications

The dc and ac analyses of a multitransistor circuit become more complex com-

pared to those for a single-transistor circuit. In this situation, a computer simulation

of the circuit, without a hand analysis, is extremely useful.

The PSpice circuit schematic is shown in Figure 6.68. The resulting

-point values

are

CQ1

= 2.54

mA,

CQ2

= 1.18

mA,

ECQ1

= 1.10

V, and

CEQ2

= 1.79

V. The ac

common-emitter current gains are

= 173

and

= 157

1 μV

sinusoidal signal is applied. The sinusoidal voltage at the collector of

51 μV

and the sinusoidal voltage at the output is 4.79 mV. The overall voltage gain

is then 4790. We will show, in later chapters, that even larger voltage gains can be ob-

tained by replacing the discrete collector resistors with active loads.

Comment: We can see from the Q-point values that the collector–emitter voltage

of each transistor is quite small. This implies that the maximum symmetrical swing

in the output voltage is limited to a fairly small value. These Q-point values can be

increased by a slight redesign of the circuit.

Discussion: The transistors used in this PSpice analysis of the circuit were standard

bipolar transistors from the PSpice library. We must keep in mind that, for the com-

puter simulation to be valid, the models of the devices used in the simulation must

match those of the actual devices used in the circuit. If the actual transistor charac-

teristics were substantially different from those used in the computer simulation, then

the results of the computer analysis would not be accurate.

EXERCISE PROBLEM

Ex 6.15: For each transistor in the circuit in Figure 6.69, the parameters are:

β = 125

(on) = 0.7

V, and

=∞

. (a) Determine the Q-points of each tran-

sistor. (b) Find the overall small-signal voltage gain

= V

. (c) Determine

the input resistance R

and the output resistance R

. (Ans. (a)

CQ1

= 0.364

mA,

CEQ1

= 7.92

CQ2

= 4.82

mA,

CEQ2

= 2.71

V (b)

=−17.7

(c)

4.76 k

= 43.7 

)

–5 V

–

0.5 kΩ

50 kΩ

1.5 kΩ

2 kΩ

5 kΩ

100 kΩ

5 kΩ

2N3904

2N3906

2 kΩ

1 mV

100 mF

5 V

–

Figure 6.68 PSpice circuit schematic for Example 6.15

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Chapter 6 Basic BJT Ampliﬁers 439

Multistage Circuit: Darlington Pair Conﬁguration

In some applications, it would be desirable to have a bipolar transistor with a much

larger current gain than can normally be obtained. Figure 6.70(a) shows a multitran-

sistor conﬁguration, called a Darlington pair or a Darlington conﬁguration, that

provides increased current gain.

The small-signal equivalent in which the input signal is assumed to be a current

source, is shown in Figure 6.70(b). We will use the input current source to determine

the current gain of the circuit. To determine the small-signal current gain

= I

we see that

π1

= I

π1

(6.103)

Therefore,

π1

= g

π1

= β

(6.104)

6.9.2

6 kΩ

70 kΩ

5 kΩ

0.2 kΩ

–

= +5 V

–

= –5 V

1.5 kΩ

10 kΩ

–

Figure 6.69 Figure for Exercise Ex 6.15

–

p 2

p 1

(a) (b)

–

Figure 6.70 (a) A Darlington pair conﬁguration; (b) small-signal equivalent circuit

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440 Part 1 Semiconductor Devices and Basic Applications

Then,

π2

= (I

+β

π2

(6.105)

The output current is

= g

π1

+ g

π2

= β

+β

(1 + β

(6.106)

where

π2

= β

. The overall current gain is then

= β

+β

(1 + β

)

∼

(6.107)

From Equation (6.107), we see that the overall small-signal current gain of the

Darlington pair is essentially the product of the individual current gains.

The input resistance is

= V

. We can write that

= V

π1

+ V

π2

= I

π1

+ I

(1 + β

π2

(6.108)

so that

= r

π1

+(1 +β

π2

(6.109)

The base of transistor Q

is connected to the emitter of Q

, which means that the

input resistance to Q

is multiplied by the factor (

1 + β

), as we saw in circuits with

emitter resistors. We can write

π1

CQ1

(6.110)

and

CQ1

∼

CQ2

(6.111)

Therefore,

π1

= β



CQ2



= β

π2

(6.112)

From Equation (6.109), the input resistance is then approximately

∼

2β

π2

(6.113)

We see from these equations that the overall gain of the Darlington pair is

large. At the same time, the input resistance tends to be large, because of the

multiplication.

Multistage Circuit: Cascode Conﬁguration

A slightly different multistage conﬁguration, called a cascode conﬁguration, is

shown in Figure 6.71(a). The input is into a common-emitter ampliﬁer (Q

), which

drives a common-base ampliﬁer (Q

). The ac equivalent circuit is shown in Fig-

ure 6.71(b). We see that the output signal current of Q

is the input signal of Q

. We

mentioned previously that, normally, the input signal of a common-base conﬁgura-

tion is to be a current. One advantage of this circuit is that the output resistance

looking into the collector of Q

is much larger than the output resistance of a simple

common-emitter circuit. Another important advantage of this circuit is in the fre-

quency response, as we will see in Chapter 7.

6.9.3

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Chapter 6 Basic BJT Ampliﬁers 441

The small-signal equivalent circuit is shown in Figure 6.72 for the case when the

capacitors act as short circuits. We see that

π1

= V

since we are assuming an ideal

signal voltage source. Writing a KCL equation at E

, we have

π1

π2

+ g

π2

(6.114)

Solving for the control voltage

π2

(noting that

π1

= V

), we ﬁnd

π2



π2

1 + β



)

(6.115)

where

= g

π2

. The output voltage is

=−(g

π2

)(R

R

)

(6.116(a))

=−g



π2

1 + β



R

(6.116(b))

Therefore, the small-signal voltage gain is

=−g



π2

1 + β



R

)

(6.117)

(a) (b)

–

Figure 6.71 (a) Cascode ampliﬁer and (b) the ac equivalent circuit

–

⎜⎜ R

–

Figure 6.72 Small-signal equivalent circuit of the cascode conﬁguration

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442 Part 1 Semiconductor Devices and Basic Applications

An examination of Equation (6.117) shows



π2

1 + β



1 + β

∼

(6.118)

The gain of the cascode ampliﬁer is then approximately

∼

−g

R

)

(6.119)

which is the same as for a single-stage common-emitter ampliﬁer. This result is to be

expected since the current gain of the common-base circuit is essentially unity.

Test Your Understanding

TYU 6.16 Consider the circuit in Figure 6.70(a). Let

β = 100

(on) = 0.7

and

=∞

for each transistor. Assume

= 10 k

= 4k

= 1

mA,

= 5

V, and

−

=−5V

. (a) Determine the Q-point values for each transistor.

(b) Calculate the small-signal hybrid-

parameters for each transistor. (c) Find the

overall small-signal voltage gain

= V

. (d) Find the input resistance R

(Ans. (a)

CQ1

= 0.0098

mA,

CEQ1

= 1.7

CQ2

= 0.990

mA,

CEQ2

= 2.4

(b)

π1

= 265 k

= 0.377 mA/V

π2

= 2.63 k

= 38.1

mA/V (c)

−77.0

(d)

= 531 k

)

TYU 6.17 Consider the cascode circuit in Figure 6.71(a). Let

β = 100

(on) = 0.7

V, and

=∞

for each transistor. Let

= 9

V and

= 10



(a) Design the circuit such that

CE1

= V

CE2

= 2.5

= 0.7

∼

mA, and

∼

0.1

mA. (Hint: Neglect the dc base currents.)

(b) Determine the small-signal hybrid-

parameters for each transistor. (c) Deter-

mine the small-signal voltage gain

= V

. (Ans. (a)

= 51



= 25



= 14



= 0.7



= 3.3



; (b)

= 38.46

mA/V,

= 2.6



;

(c)

=−94.5)

6.10 POWER CONSIDERATIONS

Objective: • Analyze the ac and dc power dissipation in a transistor

ampliﬁer and understand the concept of signal power gain.

As mentioned previously, an ampliﬁer produces a small-signal power gain. Since

energy must be conserved, the question naturally arises as to the source of this

“extra” signal power. We will see that the “extra” signal power delivered to a load is

a result of a redistribution of power between the load and the transistor.

Consider the simple common-emitter circuit shown in Figure 6.73 in which

an ideal signal voltage source is connected at the input. The dc power supplied

by the V

voltage source P

, the dc power dissipated or supplied to the collec-

tor resistor P

, and the dc power dissipated in the transistor P

are given,

respectively, as

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Chapter 6 Basic BJT Ampliﬁers 443

= I

+ P

Bias

(6.120(a))

= I

(6.120(b))

and

= I

CEQ

+ I

BEQ

∼

CEQ

(6.120(c))

The term

Bias

is the power dissipated in the bias resistors R

and R

. Normally in a

transistor

 I

, so the power dissipated is primarily a function of the collector

current and collector–emitter voltage.

If the signal voltage is given by

= V

cos ωt

(6.121)

then the total base current is given by

= I

cos ωt = I

+ I

cos ωt

(6.122)

and the total collector current is

= I

+β I

cos ωt = I

+ I

cos ωt

(6.123)

The total instantaneous collector-emitter voltage is

= V

−i

= V

−(I

+ I

cos ωt)R

= V

CEQ

− I

cos ωt

(6.124)

The average power, including ac signals, supplied by the voltage source V

given by

¯p



·i

dt + P

Bias



· [I

+ I

cos ωt] dt + P

Bias

= V



cos ωtdt+ P

Bias

(6.125)

–

Figure 6.73 Simple common-emitter ampliﬁer for power calculations

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444 Part 1 Semiconductor Devices and Basic Applications

Since the integral of the cosine function over one period is zero, the average power

supplied by the voltage source is the same as the dc power supplied. The dc voltage

source does not supply additional power.

The average power delivered to the load R

is found from

¯p



dt =



+ I

cos ωt]



dt +



cos ωtdt+



cos

ωtdt

(6.126)

The middle term of this last expression is again zero, so

¯p

= I

(6.127)

The average power delivered to the load has increased because of the signal source.

This is expected in an ampliﬁer.

Now, the average power dissipated in the transistor is

¯p



· v



+ I

cos ωt] ·[V

CEQ

− I

cos ωt] dt

(6.128)

which produces

¯p

= I

CEQ

−



cos

ωtdt

(6.129(a))

¯p

= I

CEQ

−

(6.129(b))

From Equation (6.129(b)), we can deduce that the average power dissipated in

the transistor decreases when an ac signal is applied. The V

source still supplies all

of the power, but the input signal changes the relative distribution of power between

the transistor and the load.

Test Your Understanding

TYU 6.18 In the circuit in Figure 6.74 the transistor parameters are:

β = 80

(on) = 0.7

V, and

=∞

. Determine the average power dissipated in R

, R

and Q for: (a)

= 0

, and (b)

= 18 cos ωt mV

. (Ans. (a)

¯p

= 8mW

¯p

= 0

¯p

= 14 mW

(b)

¯p

= 13.0mW

¯p

= 0.479 mW

¯p

= 8.48 mW

)

TYU 6.19 For the circuit in Figure 6.75, the transistor parameters are:

β = 100

(on) = 0.7

V, and

=∞

. (a) Determine R

such that the Q-point is in the

center of the load line. (b) Determine the average power dissipated in R

and Q for

= 0

. (c) Considering the maximum symmetrical swing in the output voltage,

determine the ratio of maximum signal power delivered to R

to the total power

dissipated in R

and the transistor. (Ans. (a)

= 2.52 k

(b)

¯p

=¯p

2.48 mW

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Chapter 6 Basic BJT Ampliﬁers 445

6.11 DESIGN APPLICATION: AUDIO AMPLIFIER

Objective: • Design a bipolar transistor audio ampliﬁer to meet a set

of speciﬁcations.

Speciﬁcations: An audio ampliﬁer is to deliver an average power of 0.1 W to an

8 

speaker from a microphone that produces a 10 mV peak sinusoidal signal and has a

source resistance of

10 k

Design Approach: A direct, perhaps brute force, approach will be taken in this

design. The generalized multistage ampliﬁer conﬁguration that will be designed is

shown in Figure 6.76. An input buffer stage, which will be an emitter-follower

circuit, is to be used to reduce the loading effect of the

10 k

source resistance. The

output stage will also be an emitter-follower circuit to provide the necessary out-

put current and output signal power. The gain stage will actually be composed of a

2-stage common-emitter ampliﬁer that will provide the necessary voltage gain. We

will assume that the entire ampliﬁer system is biased with a 12 volt power supply.

Solution (Input Buffer Stage): The input buffer stage, an emitter-follower

ampliﬁer, is shown in Figure 6.77. We will assume that the transistor has a current

gain of

= 100

. We will design the circuit so that the quiescent collector current

CQ1

= 1

mA, the quiescent collector-emitter voltage is

CEQ1

= 6

V, and

R

= 100 k

= 2 kΩ

2 kΩ

= +12 V

0.5 kΩ

30 kΩ

125 kΩ

–

Figure 6.74 Figure for Exercise TYU 6.18

= +5 V

10 kΩ

= 53.8 kΩ

–

Figure 6.75 Figure for Exercise TYU 6.19

–

= 8 Ω

= 10 kΩ

Buffer

stage

Gain

stage

Output

stage

Figure 6.76 Generalized multistage ampliﬁer for design application

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446 Part 1 Semiconductor Devices and Basic Applications

We ﬁnd

∼

− V

CEQ1

CQ1

12 − 6

= 6k

We obtain

π1

CQ1

(100)(0.026)

= 2.6k

We also have, neglecting the loading effect of the next stage,

= R

R

[r

π1

+(1 +β

]

= 100[2.6 +(101)(6)] = 85.9k

The small-signal voltage gain, from Equation (6.68) and assuming that

=∞

,is

(again neglecting the loading effect from the next stage)

(1 + β

π1

+(1 +β



+ R



(101)(6)

2.6 + (101)(6)



85.9

85.9 + 10



= 0.892

For a 10 mV peak input signal voltage, the peak voltage at the output of the buffer

stage is now

= 8.92

mV.

We ﬁnd the bias resistors to be

= 155 k

and

= 282 k

Solution (Output Stage): The output stage, another emitter-follower ampliﬁer cir-

cuit, is shown in Figure 6.78. The

8 

speaker is capacitively coupled to the output of the

ampliﬁer. The coupling capacitor ensures that no dc current ﬂows through the speaker.

For an average power of 0.1 W to be delivered to the load, the rms value of the

load current is found from

= i

(rms) · R

0.1 = i

(rms) · 8

which yields

(rms) = 0.112 A

. For a sinusoidal signal, the peak output current is then

(peak) = 0.158 A

= 10 kΩ

= 12 V

–

Figure 6.77 Input signal source and input buffer stage (emitter-follower) for design

application

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Chapter 6 Basic BJT Ampliﬁers 447

and the peak output voltage is

(peak) = (0.158)(8) = 1.26 V

We will assume that the output power transistor has a current gain of

= 50

We will set the quiescent transistor parameters at

EQ4

= 0.3 A and V

CEQ4

= 6V

Then

− V

CEQ4

EQ4

12 − 6

0.3

= 20 

We ﬁnd

CQ4



1 + β



· I

EQ4





(0.3) = 0.294 A

Then

π4

CQ4

(50)(0.026)

0.294

= 4.42 

The small-signal voltage gain of the output stage is

(1 + β

)(R

R

)

π4

+(1 +β

)(R

R

)

(51)(208)

4.42 + (51)(208)

= 0.985

which is very close to unity, as we would expect. For a required peak output voltage

= 1.26

V, we then need a peak voltage at the output of the gain stage to be

= 1.28

Solution (Gain Stage): The gain stage, which will actually be a two-stage

common-emitter ampliﬁer, is shown in Figure 6.79. We will assume that the buffer

stage is capacitively coupled to the input of the ampliﬁer, the two stages of the am-

pliﬁer are capacitively coupled, and the output of this ampliﬁer is directly coupled to

the output stage.

= 12 V

= 8 Ω

Figure 6.78 Output stage (emitter-follower) for design application

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