Neamen D. Microelectronics: Circuit Analysis and Design

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788 Part 2 Analog Electronics

The common-mode rejection ratio is then

CMRR =



(R

)

(11.86)

This result is essentially the same as the BJT diff-amp.

Effect of g

Mismatch—Two-Sided Output

We can consider the effect of transistor mismatch by considering the effect of a

mismatch in the transconductance g

. We assume g

and g

are the transconduc-

tance parameters of the two transistors in the diff-amp. We will assume that we can

write

= g

+g

and

= g

−g

Again, using the small-signal equiva-

lent circuit shown in Figure 11.23, we ﬁnd the differential-mode voltage gain is

= g

(11.87(a))

and the common-mode gain is

(2g

)

1 + 2R

(11.87(b))

The common-mode rejection ratio now becomes

CMRR =



1 + 2R

2(g

)

(11.88)

The CMRR of mismatched elements in the MOSFET diff-amp is identical with the

results of mismatched elements in the BJT diff-amp.

JFET Differential Ampliﬁer

Figure 11.25 shows a basic JFET differential pair biased with a constant-current

source. If a pure differential-mode input signal is applied such that

=+v

and

=−v

, then drain currents I

and I

increase and decrease, respectively, in

exactly the same way as in the MOSFET diff-amp.

11.3.5

–

Figure 11.25 Basic JFET

differential pair conﬁguration

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Chapter 11 Differential and Multistage Ampliﬁers 789

We can determine the differential-mode voltage gain by analyzing the small-signal

equivalent circuit. Figure 11.26 shows the equivalent circuit, with the output resistance

of the constant-current source and the small-signal resistances of Q

and Q

assumed to

be inﬁnite. The small-signal equivalent circuit of the JFET diff-amp is identical to that

of the MOSFET diff-amp in Figure 11.23 for the case when the current-source output

resistance is inﬁnite. A KCL equation at the common-source node, in phasor notation, is

gs1

+ g

gs2

= 0

(11.89(a))

gs1

=−V

gs2

(11.89(b))

The differential-mode input voltage is

≡ V

− V

= V

gs1

− V

gs2

=−2V

gs2

(11.90)

A one-sided output at V

is given by

=−g

gs2

=−g



−V



(11.91)

and the differential-mode voltage gain is

(11.92)

The expression for the differential-mode voltage gain for the JFET diff-amp

(Equation (11.92)) is exactly the same as that of the MOSFET diff-amp (Equa-

tion 11.82(a)). If the constant-current source output resistance is ﬁnite, then the JFET

diff-amp will also have a nonzero common-mode voltage gain.

Test Your Understanding

TYU 11.7 The circuit parameters of the diff-amp shown in Figure 11.19 are

= 3

−

=−3

= 0.40

mA, and

= 7.5



. The transistor parameters

are

= 0.5



= 100 μ

A/V

, and

λ = 0

. (a) Design the transistor

W/L

ratio

such that the differential voltage gain is

= 12

. (b) What is the maximum positive

common-mode voltage that can be applied such that the transistors remain biased in

the saturation region. (Ans. (a)

W/L = 256

, (b)

= 2

gs1

gs2

gs1

+–

gs2

+–

= –

–

Figure 11.26 Small-signal equivalent

circuit, JFET differential ampliﬁer

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790 Part 2 Analog Electronics

TYU 11.8 Consider the differential ampliﬁer in Figure 11.20. The transistor parame-

ters are given in Example 11.8, except that

λ = 0.02 V

−1

for M

and M

. Determine

the differential voltage gain

= v

, the common-mode gain

= v

and the CMRR

. (Ans.

= 2.74

=−0.0925

, CMRR

= 29.4

dB)

TYU 11.9 The diff-amp in Figure 11.19 is biased at

= 100 μ

A. The transistor

parameters are



= 100 μ

A/V

and

W/L = 10

. (a) If the output resistance of the

current source is

= 1



, determine the common-mode rejection ratio

CMRR

. (b) Determine the required value of

such that

CMRR

= 80

dB.

(Ans. (a)

CMRR

= 50

dB, (b)

= 31.6

)

*TYU 11.10 The differential ampliﬁer in Figure 11.20 is to be redesigned.The current-

source biasing is to be replaced with the cascode current source in Figure 11.24. The

reference current is

REF

= 100 μA

and

for transistors in the current source circuit

is 0.01 V

−1

. The parameters of the differential pair M

and M

are the same as

described in Example 11.8. The range of the common-mode input voltage is to

−4 ≤ v

≤+4V

. Redesign the diff-amp to achieve the highest possible

differential-mode voltage gain. Determine the values of A

, A

, and CMRR

. (Ans.

= 9.90

= 0.0003465

, CMRR

= 89.1

dB)

11.4 DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD

Objective: • Analyze the characteristics of BJT and FET differential

ampliﬁers with active loads.

In Chapter 10, we considered an active load in conjunction with a simple transis-

tor ampliﬁer. Active loads can also be used in diff-amp circuits to increase the

differential-mode gain.

Active loads are essentially transistor current sources used in place of resistive

loads. The transistors in the active load circuit are biased at a Q-point in the forward-

active mode as shown in Figure 11.27. A change in collector current is induced by the

differential-pair, which, in turn, produces a change in the emitter–collector voltage as

shown in the ﬁgure. The relation between the change in current and change in volt-

age is proportional to the small-signal output resistance r

of the transistor. The value

of r

is, in general, much larger than that of a discrete resistive load, so the small-

signal voltage gain will be larger with the active load.

Q-point

slope =

= constan

Figure 11.27 Current–voltage characteristic of active load device

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Chapter 11 Differential and Multistage Ampliﬁers 791

BJT Diff-Amp with Active Load

Figure 11.28 shows a differential ampliﬁer with an active load. Transistors Q

and Q

are the differential pair biased with a constant current I

, and transistors Q

and Q

form the load circuit. From the collectors of Q

and Q

, we obtain a one-sided output.

If we assume all transistors are matched, then a pure applied common-mode

voltage means that

= v

, and current I

splits evenly between Q

and

. Neglecting base currents,

= I

through the current-source circuit and

= I

with no load connected at the output.

11.4.1

–

= v

Figure 11.28 BJT differential ampliﬁer with

active load

–

Gain

stage

= v

Figure 11.29 BJT differential ampliﬁer with three-

transistor active load and second gain stage

In actual diff-amp circuits, base currents are not zero. In addition, a second

ampliﬁer stage is connected at the diff-amp output. Figure 11.29 shows a diff-amp

with an active load circuit, corresponding to a three-transistor current source, as well

as a second amplifying stage. In general, the common–emitter current gain

is a

function of collector current, as was shown in Figure 6.21(c). However, for simplic-

ity, we assume all transistor current gains are equal, even though the current level in

is much smaller than in the other transistors. Current I

is the dc bias current from

the gain stage. Assuming all transistors are matched and

= v

, current

splits evenly and

= I

. To ensure that Q

and Q

are biased in the forward-

active mode, the dc currents must be balanced, or

= I

. We see that

= I

+ I

(11.93)

Then

1 + β

+ I

β(1 +β)

(11.94)

If the base currents and I

are small, then

+ I

∼

(11.95)

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792 Part 2 Analog Electronics

Therefore,

∼

β(1 +β)

(11.96)

For the circuit to be balanced, that is, for

= I

and

= I

, we must have

= I

β(1 +β)

(11.97)

Equation (11.97) implies that the second amplifying stage must be designed and

biased such that the direction of the dc bias current is as shown and is equal to the

result of Equation (11.97). To illustrate this condition, we will analyze a second

amplifying stage using a Darlington pair, later in this chapter.

Small-Signal Analysis of BJT Active Load

Figure 11.30 shows a diff-amp with a three-transistor active load circuit. The resis-

tance R

represents the small-signal input resistance of the gain stage. We will assume

that a pure differential-mode input voltage is applied as shown in the ﬁgure. From

previous results, we know that the common-emitter terminals of Q

and Q

are at sig-

nal ground. The signal voltage at the base of Q

produces a signal collector current

= (g

)/2

, where g

is the transistor transconductance for both Q

and Q

Assuming the base currents are negligible, a signal current

= i

is induced in Q

and the current mirror produces a signal current i

equal to i

. The signal voltage at the

base of Q

produces a signal collector current

= (g

)/2

, with the direction

shown. The two signal currents, i

and i

, add to produce a signal current in the load

resistance R

. The discussion is a ﬁrst-order evaluation of the circuit operation.

11.4.2

–

Signal

ground

Figure 11.30 BJT differential ampliﬁer with three-transistor active load, showing

the signal currents

From the above discussion, we know the induced currents in Q

and Q

. To

more accurately determine the output voltage, we need to consider the equivalent

small-signal collector–emitter output circuit of the two transistors. Figure 11.31(a)

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Chapter 11 Differential and Multistage Ampliﬁers 793

shows the small-signal equivalent circuit at the collector nodes of Q

and Q

. The

circuit can be rearranged to combine the signal grounds at a common point, as in

Figure 11.31(b). From this ﬁgure, we determine that

= 2





r

R

)

(11.98)

and the small-signal differential-mode voltage gain is

= g

r

R

)

(11.99)

Equation (11.99) can be rewritten in the form

+ g

+ G

(11.100)

We recall that

= I

/2V

, r

= V

, and

= V

. The parameters g

, and G

are the corresponding conductances. Assuming

= I

, we can

write Equation (11.100) in the form

(11.101)

This expression of the differential-mode voltage gain of the diff-amp with an active

load is very similar to that obtained in the last chapter for a simple ampliﬁer with an

active load.

The output resistance looking back into the common collector node is

r

. To minimize loading effects, we need

> R

. However, since R

is gener-

ally large for active loads, we may not be able to satisfy this condition. We can de-

termine the severity of the loading effect by comparing R

and R

(a) (b)

Figure 11.31 (a) Small-signal equivalent circuit BJT differential ampliﬁer with active load

and (b) rearrangement of small-signal equivalent circuit

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794 Part 2 Analog Electronics

EXAMPLE 11.10

Objective: Determine the differential-mode gain of a diff-amp with an active load,

taking loading effects into account.

Consider the diff-amp in Figure 11.30, biased with

= 0.20

mA. Assume an

Early voltage of

= 100

V for all transistors. Determine the open-circuit (

=∞

)

differential-mode voltage gain, as well as the differential-mode voltage gain when

= 100 k

Solution: From Equation (11.101), the open-circuit voltage gain becomes

0.026

100

= 1923

When

= 100 k

, the voltage gain is

0.20 × 10

−3

2(0.026)

0.20 × 10

−3

2(100)

0.20 × 10

−3

2(100)

100 × 10

which can be written

0.20

2(0.026)

0.20

2(100)

0.20

2(100)

100

3.85

0.001 + 0.001 +0.01

= 321

An inspection of this last equation shows that the external load factor, 1/R

, domi-

nates the denominator term and thus has a tremendous inﬂuence on the gain.

Comment: The open-circuit differential-mode voltage gain, for a diff-amp with an

active load, is large. However, a ﬁnite load resistance R

causes severe loading

effects, as shown in this example. A

100 k

load caused almost an order of magni-

tude decrease in the gain.

EXERCISE PROBLEM

Ex 11.10: The diff-amp circuit in Figure 11.30 is biased at

= 0.4

mA. The

transistor parameters are

β = 120

= V

= 150

V, and

= V

= 90

(a) Determine the open-circuit (

=∞)

differential-mode voltage gain. (b) Find

the differential-mode voltage gain when

= 250



. (c) Determine the

differential-mode input resistance. (d) Find the output resistance looking back

from the load

. (Ans. (a) 2163, (b) 1018, (c) 31.2 k



, (d) 281 k

)

MOSFET Differential Ampliﬁer with Active Load

We can use an active load in conjunction with a MOSFET differential pair, as we did

for the bipolar differential ampliﬁer. Figure 11.32 shows a MOSFET diff-amp with

an active load. Transistors M

and M

are n-channel devices and form the differential

11.4.3

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Chapter 11 Differential and Multistage Ampliﬁers 795

pair biased with I

. The load circuit consists of transistors M

and M

, both p-channel

devices, connected in a current mirror conﬁguration. A one-sided output is taken

from the common drains of M

and M

. When a common-mode voltage of

= v

is applied, the current I

splits evenly between M

and M

, and

= i

= I

. There are no gate currents; therefore,

= i

and

= i

If a small differential-mode input voltage

= v

−v

is applied, then from

Equation (11.66) and (11.67), we can write

(11.102(a))

and

−i

(11.102(b))

where i

is the signal current. For small values of v

, we have

= (g

)/2

. Since

and M

are in series, we see that

= i

(11.103)

Finally, the current mirror consisting of M

and M

produces

= i

(11.104)

Figure 11.33 is the ac equivalent circuit of the diff-amp with active load, showing the

signal currents. The negative sign for i

in Equation (11.102(b)) shows up as a

change in current direction in M

, as indicated in the ﬁgure.

Figure 11.34(a) shows the small-signal equivalent circuit at the drain node of M

and M

. If the output is connected to the gate of another MOSFET, which is equiva-

lent to an inﬁnite impedance at low frequency, the output terminal is effectively an

open circuit. The circuit can be rearranged by combining the signal grounds at a

common point, as shown in Figure 11.34(b). Then,

= 2





r

)

(11.105)

–

Figure 11.32 MOSFET differential ampliﬁer with active load

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796 Part 2 Analog Electronics

and the small-signal differential-mode voltage gain is

= g

r

)

(11.106)

Equation (11.106) can be rewritten in the form

+ g

(11.107)

If we recall that

= 2

√



= λ

DQ2

= (λ

)/2

, and

DQ4

= (λ

)/2

, then Equation (11.107) becomes



(λ

+λ

)

= 2



+λ

(11.108)

DESIGN EXAMPLE 11.11

Objective: Design a MOSFET diff-amp with the conﬁguration in Figure 11.32 to

meet the speciﬁcations of the experimental system in Example 11.4.

Design Approach: We need not only to try to obtain the necessary differential-mode

gain and minimize the common-mode gain in our design, but we must also be

cognizant of the swing in the output voltage. In the circuit in Figure 11.32, if the cor-

responding PMOS and NMOS transistors are matched, then the quiescent value of

SD4

is equal to

SG4

= V

SG3

. As the signal output voltage increases, the source-to-

drain voltage of M

decreases. The minimum value of this voltage such that M

remains biased in the saturation region is

SD4

(min) = V

SD4

(sat) = V

+ V

This means that the maximum swing in the output voltage is equal to the magnitude

of the threshold voltage of M

. In this example, the maximum swing in the output

voltage is 0.8 V, so that the magnitude of the threshold voltages of the PMOS devices

must be greater than 0.8 V. Assume that NMOS devices are available with the fol-

lowing parameters:

= 0.5



= 80 μA/V

, and

= 0.02 V

−1

. Assume that

(a)

(b)

Figure 11.34 (a) Small-signal equivalent circuit, MOSFET differential

ampliﬁer with active load and (b) rearranged small-signal equivalent

circuit

–

Signal

ground

Figure 11.33 The ac equivalent circuit,

MOSFET differential ampliﬁer with

active load

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Chapter 11 Differential and Multistage Ampliﬁers 797

PMOS devices are available with the following parameters:

=−1.0



40 μA/V

, and

= 0.02 V

−1

. Choose supply voltages of

±5

V and choose a bias

current of approximately

= 200 μA

Figure 11.35 is the diff-amp and current-source network used for the design in

this example.

MbreakN-X5

MbreakP

Mbreakp

MbreakN-X4

MbreakN-X3

MbreakN-X2

MbreakN-X1 MbreakN-X

–

4 mV

2.5 V

–

2.5 V

–4 mV

–

5 V

–

5 V

–

Figure 11.35 CMOS differential ampliﬁer and current source network for Example 11.11

Design, Differential Ampliﬁer: Differential-Mode Gain:

From Equation (11.108),

the differential-mode gain is

= 2











+λ

100 = 2









200

0.02 + 0.02

which yields a width-to-length ratio of

(W/L)

= 10

for the NMOS differential pair.

Since the width-to-length ratios of the other transistors do not directly affect the gain

of the diff-amp, we may arbitrarily choose width-to-length ratios of 10 for all other

transistors except M

and M

. The W/L ratio of 10 means that the other devices are

reasonably small and do not lead to a large circuit area.

Design, Current-Source Network: For the transistor M

in the current source, we have



· (V

GS3

− V

)

200 =

(10)(V

GS3

−0.5)

which means that the required gate-to-source voltage of M

GS3

= 1.21

V. We

may choose M

and M

to be identical so that the current in the reference portion of

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