Neamen D. Microelectronics: Circuit Analysis and Design

Подождите немного. Документ загружается.

808 Part 2 Analog Electronics

and the KCL equation is

π7

π6

+ g

π6

(11.122(a))

π7

= r

π7



(1 + β)

π6



π6

= r

π7

(1 + β)I

(11.122(b))

where

π6

= β

. Substituting Equations (11.122(b)) and (11.121) into Equa-

tion (11.120), we obtain

= I

π6

π7

(1 + β)I

(11.123)

The input resistance is therefore

= r

π6

π7

(1 + β)

(11.124)

Assuming

= I

, the hybrid-π parameters are

π7

βV

(11.125(a))

and

π6

βV

(1 + β)βV

(11.125(b))

Combining Equations (11.125(a)), (11.125(b)), and Equation (11.124) yields an

expression for the input resistance, as follows:

(1 + β)βV

2(1 + β)βV

(11.126)

We can determine the small-signal voltage gain of the Darlington pair circuit by

using the small-signal equivalent circuit in Figure 11.47(b). We see that

= i

= (βi

= β(1 +β)i

(11.127)

and

(11.128)

The small-signal voltage gain is therefore

β(1 +β)R

(11.129)

Substituting Equation (11.126) into (11.129), we ﬁnd that

β(1 +β)R

2(1 + β)βV





(11.130)

In Figure 11.46, we see that resistance R

is the parallel combination of the

resistance looking into the collector of Q

and the resistance looking into the base of

. From Chapter 10, the resistance looking into the collector of Q

c11

= r

o11

(1 + g

m11



)

(11.131)

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 808 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

Chapter 11 Differential and Multistage Ampliﬁers 809

where



= r

π11

R

. The resistance looking into the base of Q

= r

π8

+(1 +β)R

. (11.132)

Equations (11.131) and (11.132) indicate that resistances R

c11

and R

are large,

which means that the effective resistance R

is also large.

EXAMPLE 11.13

Objective: Calculate the input resistance and the small-signal voltage gain of a

Darlington pair.

Consider the circuit shown in Figure 11.46, with parameters

= I

0.2 mA,

= 1

mA,

= 10 k

, and

= 0.2k

. Assume

β = 100

for all tran-

sistors, and the Early voltage for Q

is 100 V.

Solution: The input resistance, given by Equation (11.126), is

2(1 + β)βV

2(101)(100)(0.026)

0.2

⇒ 2.63 M

The small-signal voltage gain is a function of R

, which in turn is a function of R

c11

and R

. We can ﬁnd that

π11

= β V

= (100)(0.026)/0.2 = 13 k

such that



= 130.2 = 0.197 k

Also

m11

= I

= 0.2/0.026 = 7.69 mA/V

and

o11

= V

= 100/0.2 = 500 k

Therefore,

c11

= r

o11

(1 + g

m11



) = 500

[

1 + (7.69)(0.197)

]

⇒ 1.26 M

We can determine that

π8

= β V

= (100)(0.026)/1 = 2.6k

Then

= r

π8

+(1 +β)R

= 2.6 +(101)(10) ⇒ 1.01 M

Consequently, resistance R

= R

c11

R

= 1.261.01 = 0.561 M

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 809 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

810 Part 2 Analog Electronics

Finally, from Equation (11.130), the small-signal voltage gain is







0.2

2(0.026)



(561) = 2158

Comment: The input resistance of the Darlington pair is in the megohm range,

which should minimize severe loading effects on the diff-amp. In addition, the small-

signal gain is large because of the active load (Q

) and the large input resistance of

the emitter-follower output stage.

EXERCISE PROBLEM

Ex 11.13: Consider the Darlington pair Q

and Q

in Figure 11.46. Determine the

current gain of the Darlington pair,

. Use the parameters described in

Example 11.13. (Ans.

(101)(100) = 1.01 ×10

)

We can use the results of Chapter 6 to determine the output resistance of the

emitter follower. The output resistance is

= R





π8

+ Z

(1 + β)



(11.133)

where Z is the equivalent impedance, or resistance, in the base of Q

. In this case,

Z = R

c11

R

, where R

is the resistance looking into the collector of Q

. Because

of the factor

(1 + β)

in the denominator, the output resistance of the emitter follower

is normally small, as previously determined.

EXAMPLE 11.14

Objective: Calculate the output resistance of the circuit in Figure 11.46.

Consider the same circuit and transistor parameters described in Example 11.13.

Assume the Early voltage of Q

is 100 V.

Solution: From Example 11.13, we have that

c11

= 1.26

M and

π8

= 2.6k

We can then determine that

100

0.2

= 500 k

Then,

Z = R

c11

R

= 1260500 = 358 k

Therefore,

= R





π8

+ Z

(1 + β)



= 10





2.6 + 358

101



= 2.63 k

Comment: The output resistance is obviously less than R

and is substantially less

than the equivalent resistance Z in the base of Q

. In a later chapter, we will examine

a Darlington pair emitter-follower output stage in which the output resistance is on

the order of 100 .

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 810 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

Chapter 11 Differential and Multistage Ampliﬁers 811

EXERCISE PROBLEM

Ex 11.14: The circuit shown in Figure 11.48 is an ac equivalent circuit of a Dar-

lington pair output stage. Assume the transistor current gains are

= 90

and

= 180

. Assuming transistor

is biased at

CQB

= 0.5

mA, determine the

output resistance

. (Ans.

= 120 )

300 kΩ

10 kΩ

Figure 11.48 Figure for Exercise Ex11.14

A BJT diff-amp with an active load can produce a small-signal differential-

mode voltage gain on the order of 10

, and the Darlington pair can also provide a

voltage gain on the order of 10

. Since the emitter follower has a gain of essentially

unity, the overall voltage gain of the op-amp circuit is on the order of 10

. This value

is typical for the low-frequency, open-loop gain of op-amp circuits.

Test Your Understanding

TYU 11.18 Consider the Darlington pair and emitter-follower portions of the circuit

in Figure 11.46. The parameters are:

= I

= 0.5

mA,

= 2

mA,

= 5k

and

= 0.1k

. For all transistors, the current gain is

β = 120

, and for Q

and Q

the Early voltage is

= 120

V. Calculate the input resistance and small-signal volt-

age gain of the Darlington pair, and the output resistance of the emitter follower.

(Ans.

= 1.51 M

= 3115

= 1.14 k

)

TYU 11.19 In the circuit in Figure 11.46, the Darlington pair and emitter-follower

transistor parameters are the same as in Exercise TYU 11.18. Determine the effective

resistance R

(see Figure 11.47(a)) such that the small-signal voltage gain is 10

(Ans.

= 104 k

)

11.7 SIMPLIFIED BJT OPERATIONAL

AMPLIFIER CIRCUIT

Objective: • Analyze a simpliﬁed multistage bipolar ampliﬁer.

An operational ampliﬁer (op-amp) is a multistage circuit composed of a differential

ampliﬁer input stage, a gain stage, and an output stage. In this section, we will

consider a simpliﬁed BJT op-amp circuit.

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 811 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

812 Part 2 Analog Electronics

Although active load devices increase the gain of an ampliﬁer, in this discussion,

we will consider resistive loads, in order to simplify the analysis and design. For the

bipolar circuit, all component values are given; we will analyze both the dc and ac

circuit characteristics.

Figure 11.49. depicts a simple bipolar operational ampliﬁer. The differential

ampliﬁer stage is biased with a Widlar current source, and a one-sided output is

connected to the Darlington pair gain stage. An emitter bypass capacitor C

included to increase the small-signal voltage gain. The output stage is an emitter

follower. In general, we want the dc value of the output voltage to be zero when the

input voltage is zero. To accomplish this, we need to insert a dc level shifting circuit

between the voltage v

and the output voltage v

19.3 kΩ

5 kΩ

11.5 kΩ

16.5 kΩ

5 kΩ

59.6 Ω

–

= –10 V

= 10 V

= R

20 kΩ

Gain Stage Output StageDifferential Amplifier

Figure 11.49 Bipolar operational ampliﬁer circuit

EXAMPLE 11.15

Objective: Analyze the dc characteristics of the bipolar op-amp circuit.

Consider the circuit in Figure 11.49. Neglect base currents and, as a simpliﬁcation,

assume

(on) = 0.7

V for all transistors except Q

and Q

in the Widlar circuit.

Solution: The reference current I

10 − 0.7 −(−10)

19.3

= 1mA

The bias current I

is determined from

= V





and is

= 0.4mA

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 812 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

Chapter 11 Differential and Multistage Ampliﬁers 813

The collector currents are then

= I

= 0.2mA

The dc voltage at the collector of Q

= 10 − I

= 10 −(0.2)(20) = 6V

With these circuit parameters, the common-mode input voltage is limited to the range

−8.6 ≤ v

≤ 6V

, which will keep all transistors biased in the forward-active mode.

The current I

is determined to be

−2V

(on)

6 − 1.4

11.5

= 0.4mA

Since base currents are assumed negligible, the current I

∼

The dc voltage at the collectors of Q

and Q

is then

= 10 − I

= 10 −(0.4)(5) = 8V

This shows us that the dc voltage V

is midway between the 10 V supply voltage

and the dc input voltage

= 6

V to Q

. This allows a maximum symmetrical

swing in the time-varying voltage at v

Transistor Q

and resistor R

form the dc voltage level shifting function. Since

= R

, we have

= I

= 0.4mA

The dc voltage at the base of Q

is found to be

= V

− V

(on) − I

= 8 −0.7 −(0.4)(16.5) = 0.7V

This relationship produces a zero dc output voltage when a zero differential-mode

voltage is applied at the input.

Finally, current I

−(−10)

= 2mA

Comment: The dc analysis of this simpliﬁed op-amp circuit proceeds in much the

same way as in previous examples. We observe that all transistors are biased in

the forward-active mode.

EXERCISE PROBLEM

Ex 11.15: Consider the simple bipolar op-amp circuit in Figure 11.49. The tran-

sistor parameters are:

β = 100

(on) = 0.7

V (except for Q

and Q

), and

=∞

. Redesign the circuit such that

= I

= 0.1

mA,

= 5

mA,

= I

= 0.6

mA,

CE1

= V

CE2

= 4

CE4

= 3

V, and

= 0

. (Ans.

32.2k

= 143 

= 0

= 67 k

= 3.17 k

= 8.5k

= 5.83 k

, and

= 2k

)

EXAMPLE 11.16

Objective: Determine the small-signal differential-mode voltage gain of the bipolar

op-amp circuit.

Consider the circuit in Figure 11.49, with transistor parameters

β = 100

and

=∞

nea80644_ch11_753-850.qxd 6/19/09 5:40 AM Page 813 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

814 Part 2 Analog Electronics

Solution: The overall differential-mode voltage gain can be written

= A

· A



−v











The overall small-signal voltage gain is the product of the individual stage gains only

if the load resistance of the following stage is taken into account.

We will rely on previous results to determine the individual voltage gains. The input

resistances to the Darlington pair R

and to the output stage R

are indicated in Figure

11.49. The one-sided differential-mode voltage gain of the diff-amp is given by

R

)

where

is the input resistance of the Darlington pair, as follows:

= r

π3

+(1 +β)r

π4

where

π4

= β V

= (100)(0.026)/0.4 = 6.5k

and

π3

∼

= (100)

(0.026)/0.4 = 650 k

Therefore,

= 650 +(101)(6.5) = 1307 k

The transistor transconductance is

0.4

2(0.026)

= 7.70 mA/V

The gain of the differential ampliﬁer stage is therefore

R

) =



7.70



[201307] = 75.8

Since the load resistance

 R

, there is no signiﬁcant loading effect of the sec-

ond stage on the diff-amp stage.

From previous results, we know the voltage gain of the Darlington pair is given by





R

)

where

= r

π5

+(1 +β)[R

π6

+(1 +β)R

]

We ﬁnd that

π5

= β V

= (100)(0.026)/0.4 = 6.5k

and

π6

= β V

= (100)(0.026)/2 = 1.3k

Therefore

= 6.5 +(101)[16.5 + 1.3 +(101)(5)] ⇒ 52.8M

Since

 R

, the output stage does not load down the gain stage, and the small-

signal voltage gain is approximately

∼







0.4

2(0.026)



(5) = 38.5

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 814 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

Chapter 11 Differential and Multistage Ampliﬁers 815

The combination of Q

and Q

forms an emitter follower, and the gain of the output

stage is

= v

∼

The overall small-signal voltage gain is therefore

= A

· A

= (75.8)(38.5)(1) = 2918

Comment: From our previous discussion, we know that the overall gain can be

increased substantially by using active loads. Yet, the analysis of this simpliﬁed

circuit provides some insight into the design of multistage circuits, as well as the

overall small-signal voltage gain of op-amp circuits.

Computer Correlation: A PSpice analysis was performed on the bipolar op-amp

circuit in Figure 11.49. The dc output voltage from this analysis was

−0.333 V

, rather than the desired value of zero. This occurred because the B–E volt-

ages were not exactly 0.7 V, as assumed in the hand analysis. A zero output voltage

can be obtained by slightly adjusting R

. The differential voltage gain was

= 2932

, which agrees very well with the hand analysis.

EXERCISE PROBLEM

Ex 11.16: Consider the simple bipolar op-amp circuit in Figure 11.49 with circuit

and transistor parameters given in Exercise Problem Ex11.15. Determine the

input resistances R

and R

, and the differential-mode voltage gain

= v

(Ans.

= 870 k

= 21.0M

= 11,729

)

Problem-Solving Technique: Multistage Circuits

1. Perform the dc analysis of the circuit to determine the small-signal parame-

ters of the transistors. In most cases BJT base currents can be neglected. This

assumption will normally provide sufﬁcient accuracy for a hand analysis.

2. Perform the ac analysis on each stage of the circuit, taking into account the

loading effect of the following stage. (In many cases, previous results of

small-signal analyses can be used directly.)

3. The overall small-signal voltage gain or current gain is the product of the

gains of the individual stages as long as the loading effect of each stage is

taken into account.

11.8 DIFF-AMP FREQUENCY RESPONSE

Objective: • Analyze the frequency response of the differential

ampliﬁer.

In Chapter 7, we considered the frequency responses of the three basic ampliﬁer

conﬁgurations. In this section, we will analyze the frequency response of the differ-

ential ampliﬁer. Since the diff-amp is a linear circuit, we can determine the frequency

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 815 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

816 Part 2 Analog Electronics

response due to: (a) a pure differential-mode input signal, (b) a pure common-mode

input signal, and (c) the total or net result, using superposition.

Due to Differential-Mode Input Signal

Consider the basic bipolar diff-amp shown in Figure 11.50(a). The input is a pure

differential-mode input signal. We know from Equation (11.24) that the small-signal

voltage v

is at signal ground when a differential-mode input signal is applied. To

determine the frequency response, we evaluate the equivalent common-emitter half-

circuit in Figure 11.50(b).

11.8.1

(a)

(b)

–

= –

–

= +

–

Figure 11.50 (a) BJT differential ampliﬁer with differential-mode input signal and

(b) equivalent common-emitter half-circuit of differential ampliﬁer

Since the diff-amp is a direct-coupled ampliﬁer, the midband voltage gain

extends to zero frequency. This one-sided midband gain is

=−g



+ R



(11.134(a))

−β R

+ R

(11.134(b))

From the high-frequency common-emitter characteristics determined in Chap-

ter 7 we know that the upper 3 dB frequency is

2π[r

R

](C

)

(11.135)

where C

is the equivalent Miller capacitance given by

= C

(1 + g

)

(11.136)

Equation (11.136) implies that, if the value of R

is fairly large, the Miller

capacitance will signiﬁcantly affect the bandwidth of the differential ampliﬁer.

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 816 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11:

Chapter 11 Differential and Multistage Ampliﬁers 817

Due to Common-Mode Input Signal

Figure 11.51(a) shows the basic diff-amp with a pure common-mode input signal.

The circuit is symmetrical, which means that resistors R

, resistors R

, and the tran-

sistors are effectively in parallel. Figure 11.51(b) is the small-signal equivalent

circuit, with the constant-current source replaced by its output resistance R

and

capacitance C

11.8.2

(a)

(b)

–

= v

–

Figure 11.51 (a) BJT differential ampliﬁer with common-mode input signal and

(b) small-signal equivalent circuit, common-mode conﬁguration

We will justify neglecting the transistor parameters

and

. The output volt-

age is

=−(2g

)





(11.137)

A KVL equation around the B–E loop produces







+ V



+2g









(11.138(a))

= V



+1 +2



1 + β



1 + sR



(11.138(b))

Solving for

and substituting the result into Equation (11.137) yields the common-

mode gain, which is

−g

+1 +

2(1 + β)



1 + sR



(11.139(a))

nea80644_ch11_753-850.qxd 6/19/09 4:37 AM Page 817 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-11: