Morgan Kaufmann, 2004. - 336 pages.
A valuable resource for anyone who needs to simulate digital designs not contained in a single chip.
Reviews: Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possible-the availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.
This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.
A valuable resource for anyone who needs to simulate digital designs not contained in a single chip.
Reviews: Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possible-the availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.
This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.