
For non-volatile random access memories (NV-RAMs; in which the stored
information is retained even if power to the chip is interrupted), ferroelectrics
serve not just as capacitors (as in the case of the DRAM, described below), but as
the memory element itself. Their principal advantages in this application are low-
voltage (1.0 V) operation, small size (about 20% of a conventional EEPROM*
cell – and cost is proportional to size once high-yield production is achieved),
radiation hardness (not just for military applications but also for satellite
communications systems) and very high speed (60 ns access time in commercial
devices, sub-nanosecond in laboratory tests on single cells).
Additional advantages offered by a NV-RAM over a conventional EEPROM
are fast write-access (530 ns) and high number of write cycles (410
13
).
The principle on which a computer memory is based is illustrated in Fig. 5.53.
The binary-coded information is stored in an array of cells addressed by
voltage pulses applied to the ‘word’ and ‘bit’ lines. The response of a particular
cell, measured by the associated electronic circuitry, determines its state.
Figure 5.53(a) indicates the situation for a ‘passive’ FeRAM (ferroelectric
random access memory). If the capacitor is in the þP state (say a ‘1’) and the
application of two V/2 voltages is sufficient to switch the polarization to the P
state, there is a resulting ‘large’ current pulse. However were the cell in the P
state (a ‘0’) then the current pulse would be very much smaller. If the state of the
cell is such that the polarization is switched then a follow-on pulse must be
applied to return it to its original state.
In practice there are complications because the ferroelectric elements do not
have a sufficiently well defined switching voltage. This can lead to unintentional
switching of elements other than the one addressed and, consequently, to an
unacceptable error rate. The problem can be overcome by coupling each memory
element with a transistor which provides the sharply defined switching voltage.
In its simplest form each node of such an ‘active’ matrix would then take the
form shown in Fig. 5.53(b). In fact, for a variety of reasons associated with the
changes which occur in the physical properties of ferroelectrics with time, the
transistor-memory cell circuitry at each node is more complex than outlined
above, but the general principles are the same.
In the case of dynamic random access memories (DRAMs) the cell is a thin
film capacitor. The state of the cell (‘0’ or ‘1’) is read by the current pulse
following an addressing voltage pulse. Because the charge stored in the capacitor
leaks away in time (t ¼ RC) then, for the information to be retained it must be
periodically refreshed, the rate of leakage determining the necessary refresh
interval.
In the conventional DRAM the capacitor dielectric is SiO
2
(e
r
5) or a
combination of SiO
2
and Si
3
N
4
(‘ONO’ film) and is formed by controlled
oxidation or nitridation of the silicon crystal. It is necessary for the memory
capacitor to have a capacitance value of approximately 30 fF (i.e. 3010
15
F)
330 DIELECTRICS AND INSULATORS
* EEPROM, electrically erasable programmable read-only memory – a ‘FLASH’ memory.