Neamen D. Microelectronics: Circuit Analysis and Design

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1128 Part 2 Analog Electronics

15.16 Consider the circuit in Figure P15.16. (a) Derive the expressions for the

magnitude and phase of the voltage transfer function. (b) Plot the phase ver-

sus frequency for

R = 10 k

and

C = 15.9nF

. [Note: this ﬁlter is referred

to as an all-pass ﬁlter in that the magnitude of the voltage gain is constant,

but the phase of the output voltage changes with frequency.]

15.17 For each of the circuits in Figures P15.17, derive the expressions for the volt-

age transfer function

T (s) =V

(s)/ V

(s)

and the cutoff frequency f

3 dB

(a) (b)

–

Figure P15.17

–

Figure P15.18

–

Figure P15.16

15.18 The circuit in Figure P15.18 is a bandpass ﬁlter. (a) Derive the expression

for the voltage transfer function

T (s)

. (b) If

= 10 k

, determine

and

such that the magnitude of the midband gain is 50 and the cutoff fre-

quencies are 200 Hz and 5 kHz.

15.19 A simple bandpass ﬁlter can be designed by cascading one-pole high-pass

and one-pole low-pass ﬁlters. Using op-amp circuits similar to those in

Figure 15.3, design a bandpass ﬁlter with cutoff frequencies of 150 Hz and

20 kHz and with a midband gain of 30 dB. Resistor values must be no larger

than 250 k



, but the input resistance must be as large as possible.

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Chapter 15 Applications and Design of Integrated Circuits 1129

15.20 The clock frequency in the switched-capacitor circuit in Figure 15.12(a) is

= 50

kHz. Find the equivalent resistance that is simulated when

(a)

C = 0.5

pF, (b)

C = 2

pF, and (c)

C = 10

pF.

15.21 In the switched-capacitor circuit in Figure 15.12(a), the voltages are

= 2V

and

= 1V

, the capacitor value is

C = 10 pF

, and the clock

frequency is

= 100 kHz

. (a) Determine the charge transferred from

during each clock pulse. (b) What is the average current that source

supplies? (c) If the “on” resistance of each MOSFET is 1000



, determine

the time required to transfer 99 percent of the charge during each half-clock

period.

D15.22 Consider the switched-capacitor ﬁlter in Figure 15.13(b). Design the circuit

for a low-frequency gain of

−10

and a cutoff frequency of 10 kHz. The

clock frequency must be 10 times the cutoff frequency and the largest ca-

pacitance is to be 30 pF. Find the required values of

, and

15.23 The circuit in Figure P15.23 is a switched-capacitor integrator. Let

30 pF

and

= 5pF

, and assume the clock frequency is 100 kHz. Also, let

= 1V

. (a) Determine the integrating

time constant. (b) Find the

change in output voltage during each clock period. (c) If

is initially un-

charged, how many clock pulses are required for

to change by 13 V?

Section 15.2 Oscillators

15.24 Consider the phase shift oscillator in Figure 15.15. (a) For

R = 20



and

C = 0.001 μ

F, determine the frequency of oscillation. What is the required

value of

? (b) Design the circuit such that the frequency of oscillation is

= 25

kHz. Let

R = 20



15.25 In the phase-shift oscillator in Figure 15.15, the capacitor at the noninvert-

ing terminal of op-amp

is replaced by a variable capacitor

. (a) Derive

the expression for the frequency of oscillation. (b) If

C =10 pF

R =10 k

and

is variable between 10 and 50 pF, determine the range of oscillation

frequency.

15.26 Consider the phase shift oscillator in Figure 15.16. (a) Determine the fre-

quency of oscillation for

R = 12



and

C = 150

pF. What is the required

value of

? (b) Design the circuit such that the frequency of oscillation is

= 22

kHz. Let

C = 0.001 μ

15.27 Analyze the phase-shift oscillator in Figure 15.16. Show that the frequency

of oscillation is given by Equation (15.46) and that the condition for oscil-

lation is given by Equation (15.47).

15.28 The circuit in Figure P15.28 is an alternative configuration of a phase-

shift oscillator. (a) Assume that

= R

≡ R

and

= C

≡C

. Show that the frequency of oscillation is

–

Figure P15.23

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1130 Part 2 Analog Electronics

√

3/RC

. (b) Assume equal magnitudes of gain in each amplifier

stage. What is the minimum magnitude of gain required in each stage to

sustain oscillation?

–

Figure P15.28

RRRR

CCC

–

Figure P15.30

*15.29 In the circuit in Figure P15.28, let

= R

≡ R

= R

≡ R

= C

≡ C

, and let

be a

variable resistance

= R

. (a) Derive the expression for the frequency of

oscillation. (b) If

= R

, determine the condition for oscillation. (c) Using

the results of part (a), determine the range in the frequency of oscillation for

R = 25



C = 0.001 μ

F, and

15 ≤ R

≤ 30



*15.30 Consider the phase-shift oscillator in Figure P15.30. (a) Derive the expres-

sion for the frequency of oscillation. (b) Determine the condition for oscil-

lation. (c) For

R = 20



, ﬁnd

and

that will produce sustained oscil-

lations at

= 22

kHz.

*15.31 Consider the phase-shift oscillator in Figure P15.30. (a) Assume the ﬁrst re-

sistor that is connected to

is a variable resistor

. Derive the expression

for the frequency of oscillation in terms of

, and

. (b) Using the re-

sults of part (a), determine the range in the frequency of oscillation for

R = 25



C = 0.001 μ

F, and

15 ≤ R

≤ 30



15.32 A Wien-bridge oscillator is shown in Figure P15.32. (a) Derive the expres-

sion for the frequency of oscillation. (b) What is the condition for sustained

oscillations?

15.33 Consider the oscillator circuit in Figure P15.33. (a) Derive the expression

for the loop gain T(s). (b) Determine the expression for the frequency of

oscillation. (c) Find the condition for oscillation.

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Chapter 15 Applications and Design of Integrated Circuits 1131

D15.34 Design the Wein-bridge oscillator in Figure 15.17 to oscillate at

= 35

kHz.

Choose appropriate component values.

D15.35 The Colpitts oscillator in Figure 15.19 is biased at

= 0.8

mA. The tran-

sistor parameters are

= 0.8

V and

= 0.7

mA/V

. Let

= 0.02 μ

and

R = 2



. Design the circuit to oscillate at

= 350

kHz.

15.36 Figure P15.36 shows a Colpitts oscillator with a BJT. Assume

and

are

both very large. Derive the expressions for the frequency of oscillation and

the condition of oscillation.

–

Figure P15.32

–

Figure P15.33

–

C → ∞

Figure P15.36

15.37 Consider the ac equivalent circuit of the Hartley oscillator in Figure 15.21.

(a) Derive the expression for the frequency of oscillation. (b) Determine the

condition for sustained oscillations.

D15.38 For the Hartley oscillator in Figure 15.21, assume

→∞

and let

= 30

mA/V. (a) Derive the expression for the frequency of oscillation.

(b) Show that the condition for oscillation is given by

R = L

= 750

kHz for

= L

= 50 μ

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1132 Part 2 Analog Electronics

15.39 Find the loop gain functions

T (s)

and

T ( jω)

, the frequency of oscillation,

and the

required for oscillation for the circuit in Figure P15.39.

15.40 Repeat Problem 15.39 for the circuit in Figure P15.40.

15.41 Repeat Problem 15.39 for the circuit in Figure P15.41.

Section 15.3 Schmitt Trigger Circuits

15.42 For the comparator in the circuit in Figure 15.26(a), the output saturation

voltages are

±9

V. Let

REF

= 5

V. Let

be a ﬁxed resistor in series with

a potentiometer. Design the circuit such that the crossover voltage can eas-

ily be varied over the range of

−2

V to

−4

V. The minimum resistance is to

be 20 k



15.43 Consider the Schmitt trigger shown in Figure 15.29(a). Assume the satu-

rated output voltages are

=+10

V and

=−10

V. The range of the

input voltage is

−5 ≤ v

≤ 5

V. Design the circuit such that the hysteresis

width is 0.4 V and the maximum current in any resistor is 0.20 mA.

15.44 The saturated output voltages of the Schmitt trigger in Figure 15.28(a) are

=+9

V and

=−9

V. The range of the input voltage is

−9 ≤ v

≤ 9

V. (a) Design the circuit whose minimum resistance is 2 k



and such that the hysteresis width is 0.2 V. (b) Using the results of part (a),

determine the maximum current in the resistors.

15.45 A Schmitt trigger circuit is shown in Figure 15.28(a). The parameters are

=+10

=−10

= 2



, and

= 48



. (a) Determine the

crossover voltages

and

. (b) Assume a sinusoidal voltage

= 10 sin

[

2π

(

)

]

V is applied at the input. During the period

33.3 ≤ t ≤ 50

ms, determine the time periods that the output is high and the

time periods that the output is low.

15.46 Consider the Schmitt trigger in Figure P15.46. Assume the saturated output

voltages are

±V

. (a) Derive the expression for the crossover voltages

and

. (b) Let

= 10 k

= 20 k

= 5k

= 20 k

= 10 V

, and

REF

= 2V

. (a) Find

and

. (b) Sketch the voltage

transfer characteristics.

15.47 The saturated output voltages are

±V

for the Schmitt trigger in Fig-

ure P15.47. (a) Derive the expressions for the crossover voltages

and

(b) If

= 12 V

REF

=−10 V

, and

= 10 k

, ﬁnd

and

such that the switching point is

=−5

V and the hysteresis width is 0.2 V.

–

Figure P15.40

–

Figure P15.41

–

Figure P15.39

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Chapter 15 Applications and Design of Integrated Circuits 1133

REF

–

Figure P15.47

20 kΩ

–

Figure P15.48

15.48 (a) Plot the voltage transfer characteristics of the comparator circuit in

Figure P15.48 assuming the open-loop gain is inﬁnite. Let the reverse Zener

voltage be

= 5.6V

and the forward diode voltage be

= 0.6

(b) Repeat part (a) for an open-loop gain of 10

. (c) Repeat part (a) for 2.5 V

applied to the inverting terminal of the comparator.

15.49 Consider the Schmitt trigger in Figure 15.30(a). (a) Derive the expression

for the switching point and crossover voltages as given in Equations (15.76)

and (15.77). (b) Let

=+12

V and

=−12

V. The minimum resis-

tance is to be 4 k



. Determine

, and

REF

such that the crossover

voltages are

=−1.5

V and

=−2

V. (c) What are the currents in

the resistors when (i)

= V

and (ii)

= V

15.50 Consider the Schmitt trigger in Figure 15.31(a). (a) Derive the expressions

for the switching point and crossover voltages, as given in Equations

(15.78) and (15.79). (b) Let

= 12 V

=−12 V

, and

= 20 k

Determine

and

REF

such that

=−1

V and

=−2

15.51 Consider the Schmitt trigger in Figure P15.51. The saturated output volt-

ages of the op-amp are

=+10

V and

=−10

V. Assume the diode

turn-on voltage is 0.7 V. The range of the input voltage is

−2 ≤ v

≤+2

(a) Determine the crossover voltages. (b) Sketch the voltage transfer char-

acteristics. (c) Determine

, and

for (i)

= 2

V and

(ii)

=−2

REF

–

Figure P15.46

Figure P15.51

= 25 k

= 75 k

= 20 k

–

15.52 The saturated output voltages of the comparator in the circuit shown in Fig-

ure 15.33 are

±10

V. Assume forward diode voltages of 0.7 V and reverse

Zener voltages of 5.6 V. The range of the input voltage is

−2 ≤ v

≤+2

(a) Find

and

such that the hysteresis width is 0.6 V. The minimum

resistance value is to be 4 k



. (b) Find

such that the maximum current

through the diodes is 0.8 mA.

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1134 Part 2 Analog Electronics

Figure P15.55

15.53 Consider the Schmitt trigger with limiter, as shown in Figure 15.34. Assume

the forward diode turn-on voltage

is 0.7 V. (a) Determine

REF

such that

the bistable output voltages at

= 0

are

±5

V. (b) Find values of

and

such that the crossover voltages are

±0.5

V. (c) Taking

, and the

100 k



resistors into account, ﬁnd

when

= 10 V

15.54 Consider the inverting Schmitt trigger with limiting network, as shown in

Figure 15.34(a). Show that the crossover voltages are those given in

Figure 15.34(b).

15.55 (a) For the Schmitt trigger with limiter in Figure P15.55(a), ﬁnd the two

output voltage values at

= 0

and the two crossover voltages. (b) Derive

the expression for the slope of

versus

for

> V

Section 15.4 Nonsinusoidal Oscillators and Timing Circuits

15.56 Consider the Schmitt trigger oscillator in Figure 15.35. The circuit parame-

ters are

= 10



= 20



= 40



, and

= 0.02 μF

. The

saturated output voltages are

±5

V. (a) Write the expressions for

as a

function of time assuming that

has switched to its high state at

t = 0

(b) Determine the frequency of oscillation and the duty cycle.

15.57 Repeat Problem 15.56 for saturated output voltages of

=+5

V and

=−10

D15.58 Design the Schmitt trigger circuit in Figure 15.35 to produce a square-wave

output signal at a frequency of

= 12 kHz

and a 50 percent duty cycle.

Choose standard component values.

15.59 Consider the circuit in Figure P15.59. The saturated output voltages of the

Schmitt trigger comparator are

±10

V. Assume that at

t = 0

, output

switches from its low state to its high state and

is uncharged. Plot

and

versus time over two periods of oscillation.

15.60 The saturated output voltages of the comparator in Figure P15.60 are

±10

V. (a) Find

such that the frequency of oscillation is 500 Hz when the

potentiometer is connected to point A. (b) Using the results of part (a),

determine the oscillator frequency when the potentiometer is connected to

point B.

(a)

–V

REF

1 kΩ

–

+(V

REF

+ 2V

)

=(V

REF

+ 2V

)

– (V

REF

+ 2V

)

= – (V

REF

+ 2V

)

(b)

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Chapter 15 Applications and Design of Integrated Circuits 1135

= 10 V

10 kΩ

100 kΩ

C =

0.01 mF

Figure P15.66

= 10 V

1 kΩ

50 kΩ

1 kΩ

C =

0.01 mF

Figure P15.67

15.61 (a) The monostable multivibrator in Figure 15.37 is to be designed to pro-

duce a

250 μ

s output pulse. Assume saturated output voltages of

±10

V, and

let

= 0.7

= 20



, and

= 12



. (b) Determine the minimum

input triggering voltage required. (c) What is the recovery time?

15.62 A monostable multivibrator is shown in Figure 15.37. The parameters are

= 20



= 1.2 μ

F, and

= R

= 20



. The saturated output

voltages are

±5

V. (a) What is the output voltage pulse width? (b) Deter-

mine the recovery time.

D15.63 Figure 15.40 shows the 555 timer connected in the monostable multivibra-

tor mode. (a) Design the circuit to provide an output pulse 60 seconds wide.

(b) Determine the recovery time.

D15.64 Design a 555 monostable multivibrator to provide a 5

s pulse. What is the

recovery time?

15.65 A 555 timer is connected in the astable mode as shown in Figure 15.41.

Design the circuit such that the frequency of oscillation is

= 80

kHz and

the duty cycle is 60 percent. Let

= 25



15.66 A 555 ICC is connected as shown in Figure P15.66. Determine the range of

oscillation frequency and the duty cycle.

15.67 Repeat Problem 15.66 for the circuit in Figure P15.67.

0.1 mF

= 0.02 mF

= 10 kΩ

= 2 kΩ

–

Figure P15.59

0.01 mF

= 10 kΩ

–

Figure P15.60

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1136 Part 2 Analog Electronics

Section 15.5 Integrated Circuit Power Ampliﬁers

15.68 The LM380 power ampliﬁer in Figure 15.42 is biased at

= 22 V

. Let

= 100

and

= 20

for the npn and pnp transistors, respectively. (a) De-

termine the quiescent collector currents in transistors

through

(b) Assume that diodes

and

and transistors

, and

are all

matched, with parameters

= 10

−13

A. For zero input voltages, determine

the quiescent currents in

, and

. (c) For no load, calculate

the quiescent power dissipated in the ampliﬁer.

15.69 An LM380 must deliver ac power to a 10



load. The maximum power dis-

sipated in the ampliﬁer must be limited to 2 W and the maximum allowed

distortion must be limited to 3 percent. Determine: (a) the maximum power

that can be delivered to the load, (b) the maximum supply voltage, and

15.70 (a) Design the bridge circuit in Figure 15.46 such that the gain magnitude of

each op-amp circuit is 12. (b) A load resistance of

= 12 

that is to dis-

sipate an average power of

= 15

W is connected to the output. Deter-

mine the peak output voltage at each op-amp and the peak current that each

op-amp must source or sink. (c) If the peak output voltage of each op-amp

is limited to

±12

V and the peak current that each op-amp can source or

sink is limited to 0.8 A, determine (i) the maximum average power that can

be delivered to the load and (ii) the optimum value of load resistance.

D15.71 Another form of the bridge power ampliﬁer is shown in Figure P15.71. This

ampliﬁer has a very high input resistance since the input is to the noninvert-

ing terminal of an op-amp. (a) Derive the expression for the voltage gain

= v

. (b) Design the circuit to provide a gain of

= 10

so that the

magnitudes of

and

are equal. Let

= 50 k

. (c) If

= 20 

and

if the average power delivered to the load is 10 W, determine the peak am-

plitude of

and

and the peak load current.

–

Figure P15.71

–

Figure P15.72

15.72 Figure P15.72 shows an audio ampliﬁer using two identical op-amps con-

nected in a bridge conﬁguration. (a) Derive the expression for the voltage

gain

= v

. (b) Design the system such that

= 12v

The largest resistor value is to be limited to 120 k



. (c) If

= 25 

and

the peak op-amp output voltages are limited to

±8

V, determine (i) the max-

imum average power that can be delivered to the load and (ii) the peak cur-

rents that each op-amp must source or sink.

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Chapter 15 Applications and Design of Integrated Circuits 1137

D15.73 (a) Design the circuit shown in Figure P15.72 such that

=−v

and the

voltage gain

= v

= 25

. The largest resistor value is to be limited to

100 k



. (b) If the peak value of each op-amp output voltage is limited to

±12

V and the peak current that each op-amp can source or sink is limited

to 1.2 A, determine (i) the maximum average power that can be delivered to

the load and (ii) the optimum load resistance. (c) If

is twice the value

found in part (b), what is the maximum average power that can be delivered

to the load?

Section 15.6 Voltage Regulators

15.74 Transistors

and

in the voltage regulator circuit in Figure P15.74 have

parameters

β = 200

(on) = 0.7V

, and

= 100 V

. The zero-current

Zener voltage is

= 6.3V

and the Zener resistance is

= 15 

Assuming an ideal op-amp, calculate the line regulation.

= 10 V

10 kΩ

90 kΩ

9.3 kΩ

–

Figure P15.74

15.75 (a) The output voltage of a voltage regulator decreases by 8 mV as the load

current changes from 0 to 2 A. If the output voltage changes linearly with

load current, determine the output resistance of the regulator. (b) If the out-

put resistance of a voltage regulator is

= 10



and the output current

changes by 1.2 A, what is the change in output voltage?

15.76 Consider the three-terminal voltage regulator in Figure 15.51, with para-

meters as given in Example 15.16. If the maximum load current is

(max) = 100 mA

, determine the minimum applied power supply voltage

that will still maintain all transistors biased in the active region.

D15.77 Consider the three-terminal voltage regulator in Figure 15.51, with Zener

diode voltages of

= 6.3V

. Assume transistor parameters of

(npn) =

(pnp) =0.6V

, and neglect base currents. (a) Determine resistance

such that

= 0.25 mA

. (b) Determine

such that

= 12 V

15.78 The three-terminal voltage regulator in Figure 15.51 has parameters as

described in Example 15.16. Assume

= 0

= 50 V

for

, and

= 15 

for

. Determine the line regulation.

15.79 The voltage regulator shown in Figure P15.79 is a variable voltage, 0 to 5 A

power supply. The transistor parameters are

β = 80

and

(

)

= 0.7

The op-amp has a ﬁnite open-loop gain of

= 5 ×10

. The zero-current

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