Neamen D. Microelectronics: Circuit Analysis and Design

Подождите немного. Документ загружается.

1168 Part 3 Digital Electronics

(b) Determine the maximum power dissipation in the logic circuit. (Ans. (a)

(W/L)

15.4

,(b)

P = 255 μ

TYU 16.6 Repeat Exercise TYU 16.5 for the NMOS logic circuit in Figure

16.19, except assume the threshold voltage of the load device is

TNL

=−0.6

(Ans. (a)

(W/L)

= 1.09

,(b)

P = 22.5 μ

16.3 CMOS INVERTER

Objective: • Analyze and design CMOS inverters.

Complementary MOS, or CMOS, circuits contain both n-channel and p-channel

MOSFETs. As we will see, the power dissipation in CMOS logic circuits is much

smaller than in NMOS circuits, which makes CMOS very attractive. We brieﬂy re-

view the characteristics of p-channel transistors, and will then analyze the CMOS in-

verter, which is the basis of most CMOS logic circuits. We will examine the CMOS

NOR and NAND gates and other basic CMOS logic circuits, covering power dissi-

pation, noise margin, fanout, and switching characteristics.

p-Channel MOSFET Revisited

Figure 16.20 shows a simpliﬁed view of a p-channel MOSFET. The p- and n-regions

are reversed from those in an n-channel device. Again, the channel length is L and the

channel width is W. Usually in any given fabrication process, the channel length is

the same for all devices, so the channel width W is the variable in logic circuit design.

Normally, in an integrated circuit, more than one p-channel device will be fabri-

cated in the same n-substrate so the p-channel transistors will exhibit a body effect.

The n-substrate is connected to the most positive potential. The source terminal may

16.3.1

= 5 V

Figure 16.18 Figure for Exercise

TYU 16.5

= 5 V

Figure 16.19 Figure for Exercise

TYU 16.6

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1168 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

Chapter 16 MOSFET Digital Circuits 1169

be negative with respect to the substrate; therefore, voltage

may exist between

the body and the source. The threshold voltage is

= V

TPO

−

√

2eε





2φ

+ V

−



2φ



= V

TPO

−γ





2φ

+ V

−



2φ



(16.30)

where

TPO

is the threshold voltage for zero body-to-source voltage, or

= 0

The parameter

is the n-substrate doping concentration and

is a potential re-

lated to the substrate doping. The parameter

is the body effect coefﬁcient.

Current–Voltage Relation

The current–voltage characteristics of the p-channel MOSFET are functions of both

the electrical and geometric properties of the device. When the transistor is biased in

the nonsaturation region, we have

≤ v

+ V

. Therefore,

= K



2(v

+ V

−v



(16.31(a))

In the saturation region, we have

≥ v

+ V

, which means that

= K

+ V

)

(16.31(b))

The gate potential is negative with respect to the source. For the p-channel

transistor to conduct, we must have

< V

, where

is negative for an

enhancement-mode device. We also see that

> |V

when the p-channel device

is conducting.

In most cases, the channel length modulation factor

has very little effect on the

operating characteristics of MOS digital circuits. Therefore, the term

is assumed to

be zero unless otherwise stated.

The transition point, which separates the nonsaturation and saturation bias

regions, is given by

= v

(sat) = v

+ V

(16.32)

The parameter

is the conduction parameter and is given by









(16.33)

Polysilicon

or metal

Oxide

Gate

p-type

semiconducto

p-source

p-drain

n-substrate

Figure 16.20 Simpliﬁed cross section of p-channel

MOSFET

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1169 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

1170 Part 3 Digital Electronics

As before, the hole mobility

and oxide capacitance

are assumed to be

constant for all devices. The hole mobility in p-channel silicon MOSFETs is approx-

imately one-half the electron mobility

in n-channel silicon MOSFETs. This

means that a p-channel device width must be approximately twice as large as that of

an n-channel device in order that the two devices be electrically equivalent (that is,

that they have the same conduction parameter values).

Small Geometry Effects

The same small geometry effects apply to the p-channel devices as we discussed for

the n-channel devices in Section 16.1.1. As with the NMOS inverters and logic cir-

cuits, we can use Equations (16.31(a)), (16.31(b)), and (16.32) as ﬁrst-order equa-

tions in the design of CMOS logic circuits. The basic operation and behavior of

CMOS logic circuits can be predicted using these ﬁrst-order equations.

DC Analysis of the CMOS Inverter

The CMOS inverter, shown in Figure 16.21, is a series combination of a p-channel

and an n-channel MOSFET. The gates of the two MOSFETs are connected together

to form the input and the two drains are connected together to form the output. Both

transistors are enhancement-mode devices. The parameters of the NMOS are de-

noted by

and

, where

> 0

, and the parameters of the PMOS are denoted

and

, where

< 0

16.3.2

–

SDP

–

SGP

DSN

GSN

PMOS:

NMOS:

, V

Figure 16.21 CMOS inverter

Figure 16.22 shows a simpliﬁed cross section of a CMOS inverter. In this

process, a separate p-well region is formed within the starting n-substrate. The

n-channel device is fabricated in the p-well region and the p-channel device is

fabricated in the n-substrate. Although other approaches, such as an n-well in a

p-substrate, are also used to fabricate CMOS circuits, the important point is that

the processing is more complicated for CMOS circuits than for NMOS circuits.

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1170 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

Chapter 16 MOSFET Digital Circuits 1171

However, the advantages of CMOS digital logic circuits over NMOS circuits justify

their use.

Voltage Transfer Curve

Figure 16.23 shows the transistor characteristics for both the n- and p-channel de-

vices. We can determine the voltage transfer characteristics of the inverter by evalu-

ating the various transistor bias regions. For

= 0

, the NMOS device is cut off,

= 0

, and

= 0

. The PMOS source-to-gate voltage is

, which means that

the PMOS is biased on the curve marked B in Figure 16.23(b). Since the only

point on the curve corresponding to

= 0

occurs at

SDP

= 0 = V

−v

,the

output voltage is

= V

. This condition exists as long as the NMOS transistor is

cut off, or

≤ V

For

= V

, the PMOS device is cut off,

= 0

, and

= 0

. The NMOS

gate-to-source voltage is

and the NMOS is biased on the curve marked A in

Figure 16.23(a). The only point on the curve corresponding to

= 0

occurs at

DSN

= v

= 0

. The output voltage is zero as long as the PMOS transistor is cut off,

SGP

= V

−v

≤|V

. This means that the input voltage is in the range

−|V

|≤v

≤ V

OutputInput

p-channel

n-channel

Output

Input

n-substrate

p-well

DDSS

(b)(a)

Figure 16.22 Simpliﬁed cross section, CMOS inverter

DSN

(sat)

DSN

= v

GSN

= V

GSN

= V

SDP

(sat)

SDP

= V

– v

SGP

= V

SGP

= |V

(a) (b)

Figure 16.23 Current–voltage characteristics, (a) NMOS transistor and (b) PMOS transistor

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1171 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

1172 Part 3 Digital Electronics

Figure 16.24 shows the voltage transfer characteristics generated thus far for

the CMOS inverter. The more positive output voltage corresponds to a logic 1,

= V

, and the more negative output voltage corresponds to a logic 0, or

= 0

. When the output is in the logic 1 state, the NMOS transistor is cut off;

when the output is in the logic 0 state, the PMOS transistor is cut off.

Ideally, the current in the CMOS inverter in either steady-state condition is zero,

which means that, ideally, the quiescent power dissipation is zero. This result is the at-

tractive feature of CMOS digital circuits. In actuality, CMOS inverter circuits exhibit a

small leakage current in both steady-state conditions, due to the reverse-biased pn junc-

tions. However, the power dissipation may be in the nanowatt range rather than in the

milliwatt range of NMOS inverters. Without this feature, VLSI would not be possible.

When the input voltage is just greater than

,or

= v

GSN

= V

the NMOS begins to conduct and the Q-point falls on the curve marked C in

Figure 16.23(a). The current is small and

DSN

∼

, which means that the NMOS

is biased in the saturation region. The PMOS source-to-drain voltage is small, so the

PMOS is biased in the nonsaturation region. Setting

= i

, we can write

GSN

− V

]

= K



2(v

SGP

+ V

SDP

−v

SDP



(16.34)

Relating the gate-to-source and drain-to-source voltages in each transistor to the inverter

input and output voltages, respectively, we can rewrite Equation (16.34) as follows:

− V

]

= K

[2(V

−v

+ V

)(V

−v

) − (V

−v

)

]

(16.35)

Equation (16.35) relates the input and output voltages as long as the NMOS is biased

in the saturation region and the PMOS is biased in the nonsaturation region.

The transition point for the PMOS is deﬁned from

SDP

(sat) = v

SGP

+ V

(16.36)

Using Figure 16.25, Equation (16.36) can be written

− V

OPt

= V

− V

IPt

+ V

(16.37(a))

OPt

= V

IPt

− V

(16.37(b))

= V

= 0

– |V

PMOS cutoff

NMOS cutoff

Figure 16.24 CMOS inverter output voltage for input voltage in either high state or low state

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1172 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

Chapter 16 MOSFET Digital Circuits 1173

where

OPt

and

IPt

are the PMOS output and input voltages, respectively, at the

transition point.

The transition point for the NMOS is deﬁned from

DSN

(sat) = v

GSN

− V

(16.38(a))

ONt

= V

INt

− V

(16.38(b))

where

ONt

and

INt

are the NMOS output and input voltages, respectively, at the

transition point.

On the basis that

is negative for an enhancement-mode PMOS, Equa-

tions (16.37(b)) and (16.38(b)) are plotted in Figure 16.25. We determine the input

voltage at the transition points by setting the two drain currents equal to each other

when both transistors are biased in the saturation region. The result is

GSN

− V

)

= K

SGP

+ V

)

(16.39)

With the gate-to-source voltages related to the input voltage, Equation (16.39) becomes

− V

)

= K

−v

+ V

)

(16.40)

For this ideal case, the output voltage does not appear in Equation (16.40), and the input

voltage is a constant, as long as the two transistors are biased in the saturation region.

Voltage

from Equation (16.40) is the input voltage at the PMOS and NMOS

transition points. Solving for

, we ﬁnd that

= v

+ V



1 +



(16.41)

For

> V

, the NMOS is biased in the nonsaturation region and the PMOS is

biased in the saturation region. Again equating the two drain currents, we have



2(v

GSN

− V

DSN

−v

DSN



= K

SGP

+ V

)

(16.42)

– |V

ONt

= V

INt

– V

OPt

= V

IPt

+ |V

Transition point locus

for PMOS

Transition point locus

for NMOS

Figure 16.25 Regions of the CMOS transfer characteristics indicating NMOS and PMOS

transistor bias conditions. The NMOS device is biased in the saturation region in areas A

and B and in the nonsaturation region in area C. The PMOS device is biased in the saturation

region in areas B and C and in the nonsaturation region in area A.

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1173 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

1174 Part 3 Digital Electronics

Also, relating the gate-to-source and drain-to-source voltages to the input and output

voltages, respectively, modiﬁes Equation (16.42) as follows:



2(v

− V

−v



= K

−v

+ V

)

(16.43)

Equation (16.43) relates the input and output voltages as long as the NMOS

is biased in the nonsaturation region and the PMOS in the saturation region.

Figure 16.26 shows the complete voltage transfer curve.

EXAMPLE 16.7

Objective: Determine the critical voltages on the voltage transfer curve of a CMOS

inverter.

Consider a CMOS inverter biased at

= 5V

with transistor parameters

= K

and

=−V

= 0.8

V. Then consider another CMOS inverter biased

= 3V

with transistor parameters

= K

and

=−V

= 0.6

Solution (V

= 5 V): The input voltage at the transition points is, from Equa-

tion (16.41),

5 + (−0.8) +

√

1(0.8)

1 +

√

= 2.5V

The output voltage at the transition point for the PMOS is, from Equation

(16.37(b)),

OPt

= V

− V

= 2.5 −(−0.8) = 3.2V

and the output voltage at the transition point or the NMOS is, from Equa-

tion (16.38(b)),

ONt

= V

− V

= 2.5 −0.8 = 1.7V

Solution (V

= 3 V): The critical voltages are

= 1.5V V

OPt

= 2.1V V

ONt

= 0.9V

OPt

ONt

– |V

Figure 16.26 Complete voltage transfer characteristics, CMOS inverter

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1174 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

Chapter 16 MOSFET Digital Circuits 1175

Comment:

The two voltage transfer curves are shown in Figure 16.27. These ﬁgures

depict another advantage of CMOS technology, that is CMOS circuits can be biased

over a relatively wide range of voltages.

EXERCISE PROBLEM

Ex 16.7: The CMOS inverter in Figure 16.21 is biased at

= 2.1V

, and the

transistor threshold voltages are

=−V

= 0.4

V. Sketch the voltage trans-

fer curve and show the critical voltages as in Figure 16.26 for (a)

= 1

(b)

= 0.5

, and (c)

= 2

. (Ans. (a)

= 1.05 V

OPt

= 1.45 V

ONt

= 0.65 V

; (b)

= 1.16 V

OPt

= 1.56 V

ONt

= 0.76 V

; (c)

0.938 V

OPt

= 1.338 V

ONt

= 0.538 V

)

Transistor Sizing

We may note that both voltage transfer curves shown in Figure 16.27 are symmetri-

cal about the switching point

. This effect is a direct consequence of the fact

that the NMOS and PMOS transistors are matched: that is,

= K

and

. In general, the process conduction parameters,



and



, are not

equal. Therefore, in order for the two transistors to be matched, we must adjust the

width-to-length ratios. In order for

= K

, we have



(W/L)

= k



(W/L)

. In

general,



< k



, so we must have

(W/L)

>(WL)

. The PMOS device must be

larger than the NMOS device to make the two devices electrically equivalent.

CMOS Inverter Currents

When the CMOS inverter input voltage is either a logic 0 or a logic 1, the current in

the circuit is zero, since one of the transistors is cut off. When the input voltage is in

2.1

0.9

(V)

3.2

1.7

0 0.8 2.5 4.2 0.6 1.5 2.4 35

(V)

(a) (b)

Figure 16.27 Voltage transfer characteristics of CMOS inverter in Example 16.7 biased at

(a)

= 5V

and (b)

= 3V

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1175 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

1176 Part 3 Digital Electronics

the range

< V

−|V

, both transistors are conducting and a current

exists in the inverter.

When the NMOS transistor is biased in the saturation region, the current in the

inverter is controlled by

GSN

and the PMOS source-to-drain voltage adjusts such

that

= i

. This condition is demonstrated in Equation (16.34). We can write

= i

= K

GSN

− V

)

= K

− V

)

(16.44(a))

Taking the square root yields



− V

)

(16.44(b))

As long as the NMOS transistor is biased in the saturation region, the square root of

the CMOS inverter current is a linear function of the input voltage.

When the PMOS transistor is biased in the saturation region, the current in the

inverter is controlled by

SGP

and the NMOS drain-to-source voltage adjusts such

that

= i

. This condition is demonstrated in Equation (16.42). Using Equa-

tion (16.43), we can write that

= i

= K

−v

+ V

)

(16.45(a))

Taking the square root yields



−v

+ V

)

(16.45(b))

As long as the PMOS transistor is biased in the saturation region, the square root of

the CMOS inverter current is also a linear function of the input voltage.

Figure 16.28 shows plots of the square root of the inverter current for two values

bias. These curves are quasi-static characteristics in that no current is diverted

into a capacitive load. At the inverter switching point, both transistors are biased in

the saturation region and both transistors inﬂuence the current. At the switching point,

the actual current characteristic does not have a sharp discontinuity in the slope. The

channel length modulation parameter

also inﬂuences the current characteristics at

the peak value. However, the curves in Figure 16.28 are excellent approximations.

Power Dissipation

In the quiescent or static state, in which the input is either a logic 0 or a logic 1, power

dissipation in the CMOS inverter is virtually zero. However, during the switching

cycle from one state to another, current ﬂows and power is dissipated. The CMOS

16.3.3

–

(a) (b)

Figure 16.29 CMOS inverter when the output switches

(a) low to high and (b) high to low

0 0.6

0.8

2.5

1.5 2.4 3 4.2 5

(V)

= i

Figure 16.28 Square root of CMOS inverter current versus

input voltage for CMOS inverters described in Example 16.7

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1176 pinnacle MHDQ-New:MHDQ134:MHDQ134-16:

Chapter 16 MOSFET Digital Circuits 1177

inverter and logic circuits are used to drive other MOS devices for which the input

impedance is a capacitance. During the switching cycle, then, this load capacitance

must be charged and discharged.

In Figure 16.29(a), the output switches from its low to its high state. The input is

switched low, the PMOS gate is at zero volts, and the NMOS is cut off. The load ca-

pacitance

must be charged through the PMOS device. Power dissipation in the

PMOS transistor is given by

= i

−v

)

(16.46)

The current and the output voltage are related by

= C

(16.47)

The energy dissipated in the PMOS device as the output switches from low to

high is



∞

dt =



∞

−v

)

= C



−C



(16.48)

which yields

= C



−C



(16.49)

After the output has switched high, the energy stored in the load capacitance is

(

. When the inverter input goes high, the output switches low, as shown in

Figure 16.29(b). The PMOS device is cut off, the NMOS transistor conducts, and the

load capacitance discharges through the NMOS device. All the energy stored in

the load capacitance is dissipated in the NMOS device. As the output switches from

high to low, the energy dissipated in the NMOS transistor is

(16.50)

The total energy dissipated in the inverter during one switching cycle is therefore

= E

+ E

= C

(16.51)

If the inverter is switched at frequency f, the power dissipated in the inverter is

P = fE

= fC

(16.52)

Equation (16.52) shows that the power dissipated in a CMOS inverter is directly pro-

portional to the switching frequency and to

. The drive in digital IC design is

toward lower supply voltages, such as 3 V or less.

The power dissipation is proportional to

. In some digital circuits, such as

digital watches, the CMOS logic circuits are biased at

= 1.5V

, so the power

dissipation is substantially reduced.

EXAMPLE 16.8

Objective: Calculate the power dissipation in a CMOS inverter.

Consider a CMOS inverter with a load capacitance of

= 2pF

biased at

= 5V

. The inverter switches at a frequency of

f = 100 kHz

nea80644_ch16_1145-1254.qxd 07/12/2009 3:37 Page 1177 pinnacle MHDQ-New:MHDQ134:MHDQ134-16: