Neamen D. Microelectronics: Circuit Analysis and Design

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1248 Part 3 Digital Electronics

D16.63 Sketch a clocked CMOS domino logic circuit that realizes the function

Y = A

B +

. Assume that both the variable and its complement are

available as input signals.

D16.64 Sketch a clocked CMOS domino logic circuit that realizes the function

Y = AB + C(D + E)

D16.65 Sketch a clocked CMOS domino logic circuit that realizes the function

Y = A(B + C)(D + E)

16.66 Consider the CMOS clocked circuit in Figure 16.44(b). Assume the

effective capacitance at the

terminal is 25 fF. If the leakage current

through the

and

transistors is

Leakage

= 2pA

when these tran-

sistors and

are cutoff, determine the time for which

will decay

by 0.5 V.

Section 16.6 Transmission Gates

16.67 The parameters of an NMOS transmission gate are

= 0.4

= 0.15

mA/V

, and

= 0.2

pF. (a) For a gate voltage of

φ = 3.3

V, d e -

termine the quasi-steady-state output voltage for (i)

= 0

, (ii)

= 3.3

and (iii)

= 2.5

V. (b) Repeat part (a) for a gate voltage of

φ = 1.8

16.68 The NMOS transistors in the circuit shown in Figure P16.68 have parameters

= 0.2

mA/V

= 0.5

λ = 0

,and

γ = 0

. (a) For gate voltages of

φ = 2.5

V, determine the quasi-steady-state output voltage for (i)

= 0

(ii)

= 2.5

V, and (iii)

= 1.8

V. (b) Repeat part (a) for gate voltages of

φ = 2.0

16.69 Consider the circuit shown in Figure P16.69. The input voltage

is either

0.1 V or 2.5 V. Assume gate voltages of

φ = 2.5

V. The threshold voltages

are

=−0.6

V for

and

= 0.4

V for all other transistors. The

width-to-length ratios are 1 for

and

, and 5 for

and

. (a) What

are the logic 1 values for

and

? (b) Design the width-to-length ratios

and

such that the logic 0 values of

and

are 0.1 V

16.70 Consider the circuit in Figure P16.70. What logic function is implemented

by this circuit? Are there any potential problems with this circuit?

= 1 pF

fff

Figure P16.68

2.5 V2.5 V

Figure P16.69

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Chapter 16 MOSFET Digital Circuits 1249

16.71 What is the logic function implemented by the circuit in Figure P16.71?

D16.72 (a) Design an NMOS pass transistor logic circuit to perform the function

Y = A + B(C + D)

. Assume that both the variable and its complement

are available as input signals. (b) Repeat part (a) for the function

Y = ABC +

16.73 Consider the circuit in Figure P16.73. (a) Determine the value of

for

φ = 2.5

V and (i)

A = B = 0

; (ii)

A = 0

B = 2.5

V; (iii)

A = 2.5

B = 0

; and (iv)

A = B = 2.5

V. (b) Repeat part (a) for

φ = 0

. (c) What is

the logic function implemented by the circuit?

16.74 What is the logic function implemented by the circuit in Figure P16.74?

16.75 Consider the circuit in Figure P16.75. (a) Determine the value of

for

(i)

A = B = 0

; (ii)

A = 2.5

B = 0

; (iii)

A = 0

B = 2

V; and

(iv)

A = B = 2.5

V. (b) What is the logic function implemented by the

circuit?

–

Figure P16.70

–

Figure P16.71

–

Figure P16.73

–

Figure P16.74

–

Figure P16.75

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1250 Part 3 Digital Electronics

3.3 V

Figure P16.79

Section 16.7 Sequential Logic Circuits

16.78 Consider the NMOS R-S ﬂip-ﬂop in Figure 16.63 biased at

= 2.5

The threshold voltages are 0.4 V (enhancement-mode devices) and

−0.6

(depletion-mode devices). The conduction parameters are

= 40 μ

A/V

= K

= 100 μ

A/V

, and

= K

= 150 μ

A/V

. If

Q =

logic 0 and

Q =

logic 1 initially, determine the voltage at

that will

cause the ﬂip-ﬂop to change states.

16.79 Figure P16.79 shows two CMOS inverters in cascade. This circuit can be

thought of as an uncoupled CMOS R/S ﬂip ﬂop. The transistor parameters

are

= K

=0.2 mA/V

=0.5V

=−0.4

V, and

=λ

Plot

and

versus

. In particular, calculate the values of

and

= 1.5

, 1.6, 1.7, and 1.8 V.

16.80 Consider the circuit in Figure P16.80. Determine the state of the outputs for

various input signals. What is the purpose of the input signal

–

Figure P16.80

–

Figure P16.76

Figure P16.77

16.76 What is the logic function implemented by the circuit in Figure P16.76?

16.77 The circuit in Figure P16.77 is a form of clocked shift register. Signals

and

are nonoverlapping clock signals. Describe the operation of the

circuit. Discuss any possible relationship between the width-to-length ratios

of the load and driver transistors for “proper” circuit operation.

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Chapter 16 MOSFET Digital Circuits 1251

CLK

Figure P16.81

CLK

–

Figure P16.82

D16.81 The circuit in Figure P16.81 is an example of a D ﬂip-ﬂop. (a) Explain the

operation of the circuit. Is this a positive- or negative-edge-triggered ﬂip-

ﬂop? (b) Redesign the circuit to make this a static ﬂip-ﬂop.

16.82 Show that the circuit in Figure P16.82 is a J–K ﬂip-ﬂop.

16.83 Reconsider the circuit shown in Figure P16.48. Show that this circuit is a

J–K ﬂip-ﬂop with

J = v

K = v

, and

CLK = v

Section 16.8 Memories: Classiﬁcations and Architectures

16.84 A 256-K memory is organized in a square array and uses the NMOS NOR

decoder in Figure 16.73(b) for the row- and column-decoders. (a) How

many inputs does each decoder require? (b) What input to the row decoder

is required to address row (i) 52, (ii) 129, and (iii) 241? (c) What input to the

column decoder is required to address column (i) 24, (ii) 165, and (iii) 203?

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1252 Part 3 Digital Electronics

16.85 (a) A 1 megabit memory is organized in a square with each memory cell

being individually addressed. Determine the number of input address lines

required for the row and column decoders. (b) If the 1 megabit memory is

organized as 250K words

× 4

bits, determine the minimum number of input

address lines required for the row and column decoders.

16.86 A 4096-bit RAM consists of 512 words of 8 bits each. Design the

memory array to minimize the number of row and column address

decoder transistors required. How many row and column address lines

are required?

16.87 Assume that an NMOS address decoder can source 250

A when the output

goes high. If the effective capacitance of each memory cell is

= 0.8pF

and the effective capacitance of the address line is

= 5pF

, determine

the rise time of the address line voltage if

= 2.7V

Section 16.9 RAM Memory Cells

16.88 Consider the NMOS RAM cell with resistor load in Figure 16.74(b).

Assume parameters values of



= 80 μ

A/V

= 0.4

= 2.5

and

R = 1



. (a) Design the width-to-length ratio of the driver transistor

such that

= 20

mV for the on transistor. (b) Consider a 16-K memory

with the cell described in part (a). Determine the standby cell current and

the total memory power dissipation for a standby voltage of

= 1.2

D16.89 A 16-K NMOS RAM, with the cell design shown in Figure 16.74(b), is to

dissipate no more than 200 mW in standby when biased at

= 2.5V

Design the width-to-length ratios of the transistors and the resistance value.

Assume

= 0.7V

and



= 35 μA/V

16.90 Consider the CMOS RAM cell and data lines in Figure 16.76 biased at

= 2.5

V. Assume transistor parameters



= 80 μ

A/V



= 35 μ

A/V

= 0.4

=−0.4

W/L = 2

(

and

)

W/L = 4

(

and

)

, and

W/L = 1

(all other transistors). If

Q = 0

and

Q = 1

, deter-

mine the steady-state values of

and

after the row has been selected.

Neglect the body effect.

16.91 Consider the CMOS RAM cell and data lines in Figure 16.76 with circuit

and transistor parameters described in Problem 16.90. Assume initially that

Q = 0

and

Q = 1

. Assume the row is selected with

X = 2.5

V and assume

the data lines, through a write cycle, are

D = 0

and

D = 2.5

V. Determine

the values of

and

just after the row select has been applied.

*16.92 Consider a general sense ampliﬁer conﬁguration shown in Figure 16.82

for a dynamic RAM. Assume that each bit line has a capacitance of 1 pF

and is precharged to 4 V. The storage capacitance is 0.05 pF, the reference

capacitance is 0.025 pF, and each is charged to 5 V for a logic 1 and to 0 V

for a logic 0. The

and

gate voltages are 5 V when each cell is

addressed and the transistor threshold voltages are 0.5 V. Determine the

bit line voltages

and

after the cells are addressed for the case when

(a) a logic 1 is stored and (b) a logic 0 is stored.

Section 16.10 Read-Only Memory

D16.93 Design a 4-word

4-bit NMOS mask-programmed ROM to produce outputs

of 1011, 1111, 0110, and 1001 when rows 1, 2, 3, and 4, respectively, are

addressed.

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Chapter 16 MOSFET Digital Circuits 1253

D16.94 Design an NMOS

16 × 4

mask-programmed ROM that provides the 4-bit

product of two 2-bit variables.

D16.95 Design an NMOS mask-programmed ROM that decodes a binary input and

produces the output for a seven-segment array. (See Figure 2.45, Chapter 2.)

The output is to be high when a particular LED is to be turned on.

Section 16.11 Data Converters

16.96 An analog signal in the range 0 to 5 V is to be converted to a digital signal

with a quantization error of less than one percent. (a) What is the required

number of bits? (b) What input voltage value represents 1 LSB? (c) What

digital output represents an input voltage of 3.5424 V?

16.97 An analog signal in the range 0 to 3.3 V is to be converted to a digital signal

with a quantization error of less than 0.5 percent. (a) What is the required

number of bits? (b) What input voltage value represents 1 LSB? (c) What

digital output represents an input voltage of 2.5321 V.

16.98 (a) What is the output voltage of the 4-bit weighted-resistor D/A in Figure

16.90 if the input is 0110? Assume

= 10



. (b) The input signal

changes to 1001. What is the output voltage?

16.99 Consider the 4-bit weighted-resistor D/A converter in Figure 16.90. Let

= 10 k

. (a) What is the maximum allowed tolerance (

percent) in the

value of

so that the maximum error in the output is limited to

LSB?

(b) Repeat part (a) for the resistor

16.100 The weighted-resistor D/A converter in Figure 16.90 is to be expanded to an 8-

bit device. (a) What are the required resistance values of the additional four

input resistors? (b) What is the output voltage if the input is 00000001?

16.101 The N-bit D/A converter with an R–2R ladder network in Figure 16.92 is to

be designed as a 6-bit D/A device. Let

REF

=−5.0V

and

R = R

5.0k

. (a) What are currents

, I

, and

? (b) The input changes

by 1 LSB. What is the change in the output voltage? (c) What is the output

voltage if the input is 010011? (d) What is the change in output voltage if

the input changes from 101010 to 010101?

16.102 The 3-bit ﬂash A/D converter in Figure 16.93 has a reference voltage of

REF

= 3.3

V. The 3-bit output is 101. What is the range of

that produces

this output?

16.103 A 6-bit ﬂash A/D converter, similar to the one in Figure 16.93, is to be fab-

ricated. How many resistors and comparators are required?

16.104 A 10-bit counting A/D converter has an analog input in the range

0 ≤v

≤

5 V and has a clock frequency of 1 MHz. (a) What is the maximum conver-

sion time? (b) If the output is 0010010010, what is the range of the input

signal

(assume a quantization error of

LSB). (c) How many clock

pulses are required to produce an output of 0100100100?

16.105 Consider the 10-bit counting A/D converter described in Problem 16.104.

(a) What is the output if the analog input is

= 3.125 V

? (b) Repeat

part (a) if

= 1.8613 V

COMPUTER SIMULATION PROBLEMS

16.106 Consider the three types of NMOS inverters shown in Figures 16.3(a),

16.5(a), and 16.7(a). Using a computer simulation, investigate the voltage

transfer characteristics and the current versus input voltage characteristics

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1254 Part 3 Digital Electronics

of the three types of inverters as a function of various width-to-length ratios

and as a function of the body effect.

16.107 Using a computer simulation, investigate the propagation delay time and

switching characteristics of a CMOS inverter by setting up a series of

CMOS inverters in cascade. Use standard transistors and assume effective

load capacitances of 0.05 pF. Determine the propagation delay time as a

function of various transistor width-to-length ratios.

16.108 Consider a three-input CMOS NAND logic circuit similar to the two-input

circuit shown in Figure 16.34(a). Using a computer simulation, investigate

the voltage transfer characteristics and switching characteristics for various

NMOS and PMOS width-to-length ratios. What is the optimum relation be-

tween the PMOS and NMOS width-to-length ratios for symmetrical switch-

ing speeds?

16.109 Using a computer simulation, investigate the

and

values in the CMOS

RAM cell shown in Figure 16.76 during read and write cycles for various

transistor width-to-length ratios. In particular, consider the relations given

by Equations (16.82) and (16.84).

DESIGN PROBLEMS

D16.110 Design a classic CMOS logic circuit that will implement the logic function

Y = A ·

(

B + C

)

+ D · E

D16.111 Design clocked CMOS logic circuits that will implement the logic func-

tions (a)

Y =

[

A · B + C · D

]

and (b)

Y =

[

A ·

(

B + C

)

+ D

]

D16.112 Design an NMOS pass logic network that implements the logic functions

described in Problem 16.111.

D16.113 Design a clocked CMOS dynamic shift register in which the output

becomes valid on the positive-going edge of a clock signal.

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Chapter

Bipolar Digital

Circuits

1255

In the previous chapter, we presented the basic concepts of MOSFET logic circuits.

In this chapter, we discuss the basic principles of bipolar logic circuits. We initially

consider emitter-coupled logic (ECL). This technology is based on the differential

ampliﬁer and is used in specialized high-speed applications.

Prior to the emergence of MOS digital technology, the bipolar digital family of

transistor–transistor logic (TTL) circuits was used extensively. TTL and low-power

Schottky TTL logic circuits are analyzed. The basic concepts of BiCMOS logic cir-

cuits are presented.

Bipolar digital circuits are now used less frequently because of their relatively

large power requirements.

PREVIEW

In this chapter, we will:

• Analyze the basic emitter-coupled logic circuits.

• Analyze and design modiﬁed emitter-coupled logic circuits.

• Analyze transistor–transistor logic circuits.

• Analyze and design Schottky and low-power Schottky transistor–transistor

logic circuits.

• Analyze BiCMOS digital logic circuits.

• As an application, design a static ECL gate to implement a speciﬁc logic

function.

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1256 Part 3 Digital Electronics

In most cases in this chapter, total instantaneous current and voltage parameters are used, even though

most analyses of logic circuits involve dc calculations.

–

BE1

BE2

Figure 17.1 Basic

differential ampliﬁer circuit

17.1 EMITTER-COUPLED LOGIC (ECL)

Objective: • Analyze the basic emitter-coupled logic circuits

The emitter-coupled logic (ECL) circuit is based on the differential ampliﬁer circuit,

which we studied in Chapter 11 in the context of linear ampliﬁers. In digital applica-

tions, the diff-amp is driven into its nonlinear region. The transistors are either cut off

or in the active region. Saturation is avoided in order to minimize switching times

and propagation delay times. ECL circuits have the shortest propagation delay times

of any bipolar digital technology.

Differential Ampliﬁer Circuit Revisited

Consider the basic diff-amp circuit in Figure 17.1. For a linear diff-amp, the differ-

ence between the two input voltages is small and both transistors remain biased

in the active region at all times. The relationship between collector currents and

base–emitter voltages for

and

can be written

= I

BE1

(17.1(a))

and

= I

BE2

(17.1(b))

where

and

are assumed to be matched and parameter

is the same for both

devices. The current–voltage transfer curves are shown in Figure 17.2.

In digital applications, the difference between the two input voltages is large,

which means that one transistor remains biased in its active region while the opposite

17.1.1

= v

BE1

– v

BE2

(volts)

0 0.05

0.5

1.0

0.10 0.15

–

0.15 – 0.10 – 0.05

Figure 17.2 Normalized dc transfer characteristics, BJT

differential ampliﬁer

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Chapter 17 Bipolar Digital Circuits 1257

transistor is cut off. For example, if

BE1

= v

BE2

+0.12

, then the ratio of

and

BE1

BE2

= e

BE1

−v

BE2

)/V

= e

0.12/0.026

= 101

(17.2)

When the base–emitter voltage of

is 120 mV greater than the base–emitter volt-

age of

, the collector current of

is 100 times that of

; for all practical

purposes,

is on and

is cut off.

Conversely, if

is less than

by at least 120 mV, then

is effectively cut off and

is on. The difference ampliﬁer, when operating as a digital circuit, operates as a cur-

rent switch. When

by at least 120 mV, it switches an approximately constant

current through

; when

by at least 120 mV, the current goes to

EXAMPLE 17.1

Objective: Calculate the currents and voltages in the basic differential ampliﬁer

circuit used as a digital circuit.

Consider the circuit in Figure 17.1. Assume that

= 2.5

−

=−2.5

= R

≡ R

= 5



= 6



, and

= 0

. Neglect base currents in the dc

analysis.

Solution: For

= v

= 0

, both transistors are on. Assume a base–emitter turn-on

voltage of 0.7 V; then

=−0.7

V and

− V

−

−0.7 − (−2.5)

= 0.3mA

Assuming

and

are matched, we have

= i

so that

= i

0.15

mA. Then

= v

= V

−i

= 2.5 −(0.15)(5) = 1.75 V

Both

and

are biased in the active region.

Now let

=−0.5

V. Since the base voltage of

is less than the base voltage

by more than 120 mV, then

is cut off and

is on. In this case,

= v

− V

(on) =−0.7

V and

= 0.3

mA, as before. However,

= 0

and

= i

= 0.3

mA, so that

= V

= 2.5

and

= V

−i

= 2.5 −

(

0.3

)(

)

= 1.0

For

=+0.5

is on and

is cut off. For this case,

= v

− V

(on) = 0.5 −0.7 =−0.2

V and the current

= i

− V

−

−0.2 − (−2.5)

= 0.383 mA

Then

= V

−i

= 2.5 −

(

0.383

)(

)

= 0.585

and

= V

= 2.5

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